专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110225256A1 Video Synchronization with Distributed Modules 有权
标题翻译：与分布式模块的视频同步
公开(公告)号：US20110225256A1
公开(公告)日：2011-09-15
申请号：US12764448
申请日：2010-04-21
申请人： Franck Seigneret , Claude Marescot , Seyed Karim Djafarian Tehrani , Maija Kuusela , Alain Bruno Chateau
发明人： Franck Seigneret , Claude Marescot , Seyed Karim Djafarian Tehrani , Maija Kuusela , Alain Bruno Chateau
IPC分类号： G06F15/16
CPC分类号： G06F9/4843
摘要： A digital system is provided that includes a number of hardware accelerators. Each hardware accelerator is paired with a synchronization module that is configured to determine when a scheduled task can be started. Each synchronization module includes a network interface configured to send and receive messages to and from other synchronization modules and a configuration interface configured to receive task information from a host processor. Each synchronization module also includes a task scheduler configured to select a task in response to a received message and a task processor interface configured to initiate the selected task on a hardware accelerator coupled to the synchronization module.
摘要翻译：提供了包括多个硬件加速器的数字系统。每个硬件加速器与配置为确定何时可以启动计划任务的同步模块配对。每个同步模块包括被配置为向和从其他同步模块发送消息和从其他同步模块接收消息的网络接口和被配置为从主机处理器接收任务信息的配置接口。每个同步模块还包括被配置为响应于接收到的消息选择任务的任务调度器和配置成在耦合到同步模块的硬件加速器上发起所选任务的任务处理器接口。

2. 发明授权

US07574584B2 Splitting execution of a floating-point add instruction between an integer pipeline for performing mantissa addition and a hardware state machine 有权
标题翻译：在执行尾数加法的整数流水线和硬件状态机之间分割浮点加法指令
公开(公告)号：US07574584B2
公开(公告)日：2009-08-11
申请号：US11186239
申请日：2005-07-21
申请人： Gerard Chauvel , Maija Kuusela
发明人： Gerard Chauvel , Maija Kuusela
IPC分类号： G06F9/00 , G06F7/42
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： In some embodiments, a processor includes fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and interacts with the integer pipeline. The instruction is executed partly in the integer pipeline according to software and partly in the hardware state machine. For a floating point add instruction, mantissa addition is executed in the integer pipeline and the plurality of operations performed by the hardware state machine includes testing of exponents, testing for overflow and underflow conditions, packing, and rounding detection.
摘要翻译：在一些实施例中，处理器包括取指令，整数流水线以及与整数流水线分开并与其整体流水线相互作用的硬件状态机。该指令根据软件部分在整数流水线中执行，部分在硬件状态机中执行。对于浮点加法指令，在整数流水线中执行尾数加法，并且由硬件状态机执行的多个操作包括指数的测试，溢出和下溢条件的测试，打包和舍入检测。

3. 发明授权

US07555611B2 Memory management of local variables upon a change of context 有权
标题翻译：改变上下文时局部变量的内存管理
公开(公告)号：US07555611B2
公开(公告)日：2009-06-30
申请号：US10632076
申请日：2003-07-31
申请人： Serge Lasserre , Maija Kuusela , Gerard Chauvel
发明人： Serge Lasserre , Maija Kuusela , Gerard Chauvel
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F2212/502 , Y02D10/13
摘要： A cache subsystem may comprise a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register. Local variables (e.g., Java local variables) may be stored in the data memory. The data memory preferably is adapted to store two groups of local variables. A first group comprises local variables associated with finished methods and a second group comprises local variables associated with unfinished methods. Further, local variables are saved to, or fetched from, external memory upon a context change based on a threshold value differentiating the first and second groups. The first value may comprise a threshold address or an allocation bit associated with each of a plurality of lines forming the data memory.
摘要翻译：缓存子系统可以包括多路组关联高速缓存和数据存储器，其保存由存储在寄存器中的地址定义的连续的存储块。局部变量（例如，Java局部变量）可以存储在数据存储器中。数据存储器优选地适于存储两组局部变量。第一组包括与完成的方法相关联的局部变量，第二组包括与未完成方法相关联的局部变量。此外，基于区分第一和第二组的阈值，在上下文改变时，将局部变量保存到外部存储器或从外部存储器获取。第一值可以包括与形成数据存储器的多条线中的每一条相关联的阈值地址或分配位。

4. 发明授权

US07058765B2 Processor with a split stack 有权
标题翻译：处理器与分离堆栈
公开(公告)号：US07058765B2
公开(公告)日：2006-06-06
申请号：US10632079
申请日：2003-07-31
申请人： Gerard Chauvel , Maija Kuusela , Serge Lasserre
发明人： Gerard Chauvel , Maija Kuusela , Serge Lasserre
IPC分类号： G06F12/08
CPC分类号： G06F9/30134 , G06F9/30101 , G06F9/3012 , G06F9/30174 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0875 , G06F12/0891 , G06F12/1036 , G06F12/126 , G06F2212/502 , G06F2212/681 , Y02D10/13
摘要： Methods and apparatuses are disclosed for implementing a processor with a split stack. In some embodiments, the processor includes a main stack and a micro-stack. The micro-stack preferably is implemented in the core of the processor, whereas the main stack may be implemented in areas that are external to the core of the processor. Operands are preferably provided to an arithmetic logic unit (ALU) by the micro-stack, and in the case of underflow (micro-stack empty), operands may be fetched from the main stack. Operands are written to the main stack during overflow (micro-stack full) or by explicit flushing of the micro-stack. By optimizing the size of the micro-stack, the number of operands fetched from the main stack may be reduced, and consequently the processor's power consumption may be reduced.
摘要翻译：公开了用于实现具有分组堆栈的处理器的方法和装置。在一些实施例中，处理器包括主堆栈和微堆栈。微堆优选地实现在处理器的核心中，而主堆栈可以在处理器核心外部的区域中实现。操作数优选地通过微栈提供给算术逻辑单元（ALU），并且在下溢（微堆空）的情况下，可以从主堆栈获取操作数。在溢出（微型堆栈完整）或通过显式冲洗微型堆栈时，操作数将写入主堆栈。通过优化微堆栈的大小，可以减少从主堆栈取出的操作数的数量，从而可以降低处理器的功耗。

5. 发明授权

US06769052B2 Cache with selective write allocation 有权
标题翻译：具有选择性写入分配的缓存
公开(公告)号：US06769052B2
公开(公告)日：2004-07-27
申请号：US10157555
申请日：2002-05-29
申请人： Gerard Chauvel , Maija Kuusela , Dominique D'Inverno
发明人： Gerard Chauvel , Maija Kuusela , Dominique D'Inverno
IPC分类号： G06F1200
CPC分类号： G06F12/0888 , G06F12/0804 , Y02D10/13
摘要： A digital system and method of operation is provided in which several processors (590n) are connected to a shared cache memory resource (500). A translation lookaside buffer (TLB) (310n) is connected to receive a request virtual address from each respective processor. A set of address regions (pages) is defined within an address space of a back-up memory associated with the cache and write allocation in the cache is defined on a page basis. Each TLB has a set of entries that correspond to pages of address space and each entry provides a write allocate attribute (550) for the associated page of address space. During operation of the system, software programs are executed and memory transactions are performed. A write allocate attribute signal (550) is provided with each write transaction request. In this manner, the attribute signal is responsive to the value of the write allocation attribute bit assigned to an address region that includes the address of the write transaction request. Write allocation in the cache memory is performed generally in accordance with the write allocate attribute signal. However, write allocation policy circuitry (560) is also provided and operates to refine the operation of the write allocation. Thus, the cache memory is responsive to the write policy circuitry such that write allocation is performed in a selective manner in accordance to the attribute signal for a first write policy state and write allocation is always performed in accordance to the attribute signal for a second write policy state.
摘要翻译：提供了数字系统和操作方法，其中多个处理器（590n）连接到共享高速缓存存储器资源（500）。连接翻译后备缓冲器（TLB）（310n）以从每个相应的处理器接收请求虚拟地址。在与高速缓存相关联的备份存储器的地址空间内定义一组地址区（页），并且以页为基础定义高速缓存中的写分配。每个TLB具有对应于地址空间的页面的一组条目，并且每个条目为相关联的地址空间页面提供写入分配属性（550）。在系统操作期间，执行软件程序并执行存储器事务。写入分配属性信号（550）被提供有每个写事务请求。以这种方式，属性信号响应于分配给包括写事务请求地址的地址区的写分配属性位的值。通常根据写入分配属性信号来执行高速缓冲存储器中的写入分配。然而，还提供了写分配策略电路（560）并且操作以改进写分配的操作。因此，高速缓冲存储器响应于写策略电路，使得根据用于第一写策略状态的属性信号以选择的方式执行写分配，并且总是根据用于第二写的属性信号执行写分配政策状态。

6. 发明授权

US07757067B2 Pre-decoding bytecode prefixes selectively incrementing stack machine program counter 有权
标题翻译：预解码字节码前缀选择性地递增堆栈机器程序计数器
公开(公告)号：US07757067B2
公开(公告)日：2010-07-13
申请号：US10632222
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Maija Kuusela
发明人： Gerard Chauvel , Serge Lasserre , Maija Kuusela
IPC分类号： G06F9/30 , G06F9/40
CPC分类号： G06F9/30149 , G06F9/30076 , G06F9/30181 , G06F9/30185 , G06F9/382 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecodes in parallel with the decoder decoding a current instruction. The pre-decoder determines if a subsequent instruction contains a prefix. If a prefix is detected in at least one of the five Bytecodes, a program counter skips the prefix and changes the behavior of the decoder during the decoding of the subsequent instruction.
摘要翻译：包括耦合到预解码器的解码器的处理器（例如，协处理器），其中解码器与预解码器并行地解码当前指令，以对后续指令进行解码。特别地，预解码器与解码器解码当前指令并行地检查至少五个字节码。预解码器确定后续指令是否包含前缀。如果在五个字节码中的至少一个中检测到前缀，则程序计数器跳过前缀，并且在后续指令的解码期间改变解码器的行为。

7. 发明授权

US07496930B2 Accessing device driver memory in programming language representation 有权
标题翻译：以编程语言表示访问设备驱动程序内存
公开(公告)号：US07496930B2
公开(公告)日：2009-02-24
申请号：US10831575
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F13/00
CPC分类号： G09G5/39 , G06F3/14 , G09G5/393
摘要： In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the application software to manage the device and also comprises instructions that map the application data structure to a memory associated with the device without the use of a device driver. In other embodiments, a method comprises initializing an application data structure to manage a hardware device and mapping the application data structure to a memory associated with the hardware device without the use of a device driver. The application data structure may store a single dimensional data structure or a multi-dimensional data structure. In some embodiments, the device being managed by the application software may comprise a display and the application software may comprise Java code.
摘要翻译：在一些实施例中，存储介质包括执行一个或多个操作并直接管理设备的应用软件。应用软件包括初始化应用软件可用于管理设备的应用数据结构（例如，对象或阵列）的指令，还包括将应用数据结构映射到与设备相关联的存储器而不使用设备驱动。在其他实施例中，一种方法包括初始化应用数据结构以管理硬件设备，并将应用数据结构映射到与硬件设备相关联的存储器，而不使用设备驱动程序。应用数据结构可以存储单维数据结构或多维数据结构。在一些实施例中，由应用软件管理的设备可以包括显示器，并且应用软件可以包括Java代码。

8. 发明申请

US20050033945A1 Dynamically changing the semantic of an instruction 审中-公开
标题翻译：动态地改变指令的语义
公开(公告)号：US20050033945A1
公开(公告)日：2005-02-10
申请号：US10830917
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banatre , Jean-Paul Routeau , Salam Majoul , Frederic Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banatre , Jean-Paul Routeau , Salam Majoul , Frederic Parain
IPC分类号： G06F9/22 , G06F9/318 , G06F9/44 , G06F11/34 , G06F12/00 , G06F9/30
CPC分类号： G06F11/3466 , G06F9/30087 , G06F9/30174 , G06F9/30189 , G06F2201/865 , G06F2201/88
摘要： A technique comprises receiving an instruction and dynamically changing the instruction's semantic based on programmable information that is separate from the instruction. The change in semantic may comprise the inclusion of monitoring code that determines a performance characteristic associated with the instruction or a change in the instruction's operation (e.g., the inclusion of read or write barrier operations to support a garbage collector).
摘要翻译：一种技术包括接收指令并基于与指令分离的可编程信息来动态地改变指令的语义。语义的变化可以包括包括确定与指令相关联的性能特征的监视代码或指令的操作的改变（例如，包括用于支持垃圾收集器的读取或写入屏障操作）。

9. 发明授权

US06751706B2 Multiple microprocessors with a shared cache 有权
标题翻译：具有共享缓存的多个微处理器
公开(公告)号：US06751706B2
公开(公告)日：2004-06-15
申请号：US09932651
申请日：2001-08-17
申请人： Gerard Chauvel , Maija Kuusela , Dominique D'Inverno , Serge Lasserre
发明人： Gerard Chauvel , Maija Kuusela , Dominique D'Inverno , Serge Lasserre
IPC分类号： G06F1200
CPC分类号： G06F9/5011 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F9/5094 , G06F11/3409 , G06F12/0292 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/815 , G06F2201/86 , G06F2201/88 , G06F2201/885 , G06F2209/5014 , G06F2209/5021 , G06F2209/507 , G06F2212/1028 , G06F2212/681 , Y02D10/13 , Y02D10/16 , Y02D10/22 , Y02D10/24 , Y02D10/34
摘要： A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. When the L2-cache misses, the penalty to access to data within the L3 memory is high. The system supports miss under miss to let a second miss interrupt a segment prefetch being done in response to a first miss. Thus, an interruptible SDRAM to L2-cache prefetch system with miss under miss support is provided. A shared translation look-aside buffer (TLB) is provided for L2 accesses, while a private TLB is associated with each processor. A micro TLB (&mgr;TLB) is associated with each resource that can initiate a memory transfer. The L2 cache, along with all of the TLBs and &mgr;TLBs have resource ID fields and task ID fields associated with each entry to allow flushing and cleaning based on resource or task. Configuration circuitry is provided to allow the digital system to be configured on a task by task basis in order to reduce power consumption.
摘要翻译：数字系统具有几个处理器，与每个处理器相关联的私有一级（L1）高速缓存，每个条目具有多个段的共享二级（L2）高速缓存以及三级（L3）物理存储器。共享的L2高速缓存体系结构体现为4路关联性，每个条目有4个段和4个有效位和脏位。当L2缓存未命中时，访问L3内存中的数据的惩罚很高。该系统支持未命中错过，以使第二个错误中断一个段预取正在响应于第一个错过。因此，提供了一个可中断的SDRAM到L2缓存预取系统，其中错过了支持。为L2访问提供共享翻译后备缓冲器（TLB），而私有TLB与每个处理器相关联。微型TLB（muTLB）与可以启动存储器传输的每个资源相关联。 L2缓存以及所有TLB和muTLB都具有与每个条目关联的资源ID字段和任务ID字段，以允许基于资源或任务的冲洗和清理。提供配置电路以允许数字系统根据任务在任务上进行配置，以便降低功耗。

10. 发明授权

US08032891B2 Energy-aware scheduling of application execution 有权
标题翻译：能源感知调度应用程序执行
公开(公告)号：US08032891B2
公开(公告)日：2011-10-04
申请号：US10151282
申请日：2002-05-20
申请人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Frédéric Parain , Jean-Paul Routeau , Salam Majoul
发明人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Frédéric Parain , Jean-Paul Routeau , Salam Majoul
IPC分类号： G06F9/46 , G06F1/32
CPC分类号： G06F9/4881 , G06F1/3228 , G06F1/329 , Y02D10/24
摘要： A mobile device (10) manages tasks (18) using a scheduler (20) for scheduling tasks on multiple processors (12). To conserve energy, the set of tasks to be scheduled are divided into two (or more) subsets, which are scheduled according to different procedures. In a specific embodiment, the first subset contains tasks with the highest energy consumption deviation based on the processor that executes the task. This subset is scheduled according to a power-aware procedure for scheduling tasks primarily based on energy consumption criteria. If there is no failure, the second subset is scheduled according to a real-time constrained procedure that schedules tasks primarily based on the deadlines associated with the various tasks in the second subset. If there is a failure in either procedure, one or more tasks with the lowest energy consumption deviation are moved from the first subset to the second subset and the scheduling is repeated.
摘要翻译：移动设备（10）使用调度器（20）管理任务（18），用于在多个处理器（12）上调度任务。为了节约能源，要调度的任务集合分为两个（或多个）子集，根据不同的过程进行调度。在具体实施例中，第一子集基于执行任务的处理器包含具有最高能量消耗偏差的任务。该子集根据用于主要基于能量消耗标准的调度任务的功率感知程序进行调度。如果没有失败，则根据实时约束程序调度第二子集，该实时约束过程主要基于与第二子集中的各种任务相关联的期限来调度任务。如果任何一个过程都有故障，则能量消耗偏差最小的一个或多个任务从第一个子集移动到第二个子集，重复调度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式