专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07840784B2 Test and skip processor instruction having at least one register operand 有权
标题翻译：测试和跳过具有至少一个寄存器操作数的处理器指令
公开(公告)号：US07840784B2
公开(公告)日：2010-11-23
申请号：US10632084
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
IPC分类号： G06F9/32
CPC分类号： G06F9/30069 , G06F9/30181 , G06F9/30185 , G06F9/30189 , G06F9/30196 , G06F9/355 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor may execute a test and skip instruction that includes or otherwise specifies at least two operands that are used in a comparison operation. Based on the results of the comparison, the instruction that follows the test and skip instruction is “skipped.” The test and skip instruction may specify that the operands used in the comparison include (1) the contents of two registers, (2) the contents of one register and the contents of a memory location, or (3) the contents of one register and a stack value. In the second mode (an operand being from memory), a register is specified in the test and skip instruction that contains a value from which a pointer may be calculated. The calculated pointer preferably points to the memory location. If a stack value is used in the execution of the test and skip instruction, the instruction may include a reference to a register that points to the top of the stack. Further, the stack pointer may be adjusted automatically if the stack is used to provide an operand for the instruction. Embodiments may include apparatus and methods.
摘要翻译：处理器可以执行包括或以其他方式指定在比较操作中使用的至少两个操作数的测试和跳过指令。根据比较结果，测试和跳过指令之后的指令被“跳过”。测试和跳过指令可以指定比较中使用的操作数包括（1）两个寄存器的内容，（2）一个寄存器的内容和存储器位置的内容，或（3）一个寄存器的内容和堆栈值。在第二模式（一个来自存储器的操作数）中，在测试和跳过指令中指定一个寄存器，该指令包含可以计算指针的值。计算出的指针最好指向存储器位置。如果在执行测试和跳过指令时使用堆栈值，则该指令可以包括对指向堆栈顶部的寄存器的引用。此外，如果堆栈用于为指令提供操作数，则可以自动调整堆栈指针。实施例可以包括装置和方法。

2. 发明授权

US07058765B2 Processor with a split stack 有权
标题翻译：处理器与分离堆栈
公开(公告)号：US07058765B2
公开(公告)日：2006-06-06
申请号：US10632079
申请日：2003-07-31
申请人： Gerard Chauvel , Maija Kuusela , Serge Lasserre
发明人： Gerard Chauvel , Maija Kuusela , Serge Lasserre
IPC分类号： G06F12/08
CPC分类号： G06F9/30134 , G06F9/30101 , G06F9/3012 , G06F9/30174 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0875 , G06F12/0891 , G06F12/1036 , G06F12/126 , G06F2212/502 , G06F2212/681 , Y02D10/13
摘要： Methods and apparatuses are disclosed for implementing a processor with a split stack. In some embodiments, the processor includes a main stack and a micro-stack. The micro-stack preferably is implemented in the core of the processor, whereas the main stack may be implemented in areas that are external to the core of the processor. Operands are preferably provided to an arithmetic logic unit (ALU) by the micro-stack, and in the case of underflow (micro-stack empty), operands may be fetched from the main stack. Operands are written to the main stack during overflow (micro-stack full) or by explicit flushing of the micro-stack. By optimizing the size of the micro-stack, the number of operands fetched from the main stack may be reduced, and consequently the processor's power consumption may be reduced.
摘要翻译：公开了用于实现具有分组堆栈的处理器的方法和装置。在一些实施例中，处理器包括主堆栈和微堆栈。微堆优选地实现在处理器的核心中，而主堆栈可以在处理器核心外部的区域中实现。操作数优选地通过微栈提供给算术逻辑单元（ALU），并且在下溢（微堆空）的情况下，可以从主堆栈获取操作数。在溢出（微型堆栈完整）或通过显式冲洗微型堆栈时，操作数将写入主堆栈。通过优化微堆栈的大小，可以减少从主堆栈取出的操作数的数量，从而可以降低处理器的功耗。

3. 发明授权

US06772326B2 Interruptible an re-entrant cache clean range instruction 有权
标题翻译：中断缓存清除范围指令
公开(公告)号：US06772326B2
公开(公告)日：2004-08-03
申请号：US10157576
申请日：2002-05-29
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno
IPC分类号： G06F944
CPC分类号： G06F9/4843 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F12/0842 , G06F12/0891
摘要： A digital system and method of operation is provided in which a method is provided for cleaning a range of addresses in a storage region specified by a start parameter and an end parameter. An interruptible clean instruction (802) can be executed in a sequence of instructions (800) in accordance with a program counter. If an interrupt (804) is received during execution of the clean instruction, execution of the clean instruction is suspended before it is completed. After performing a context switch (810), the interrupt is serviced (820). Upon returning from the interrupt service routine (830, 834), execution of the clean instruction is resumed by comparing the start parameter and the end parameter provided by the clean instruction with a current content of a respective start register and end register used during execution of the clean instruction. If the same, execution of the clean instruction is resumed using the current content of the start register and end register. If different, execution of the clean instruction is restarted by storing the start parameter provided by clean instruction in the start register and by storing the end parameter in the end register. In this manner, no additional context information needs to be saved during a context switch in order to allow the clean instruction to be interruptible. If the interrupt occurred during a non-interruptible instruction, then the instruction is completed before the context switch and a return (830, 832) after the interrupt service routine begins execution at the next instruction (803). Other instructions that perform a sequence of operations can also be made interruptible in a similar manner.
摘要翻译：提供了一种数字系统和操作方法，其中提供了一种用于清洁由起始参数和结束参数指定的存储区域中的地址范围的方法。根据程序计数器，可以以指令序列（800）执行中断清除指令（802）。如果在执行干净指令期间接收到中断（804），干净指令的执行将在完成之前暂停。执行上下文切换（810）后，中断服务（820）。在从中断服务程序（830,834）返回时，通过将清除指令提供的开始参数和结束参数与执行期间使用的相应起始寄存器和结束寄存器的当前内容进行比较来恢复干净指令的执行干净的说明。如果相同，则使用起始寄存器和结束寄存器的当前内容恢复干净指令的执行。如果不同，通过将清除指令提供的启动参数存储在起始寄存器中并通过将结束参数存储在结束寄存器中来重新启动干净指令的执行。以这种方式，在上下文切换期间不需要保存附加上下文信息，以便允许清除指令是可中断的。如果在不可中断指令期间发生中断，则在中断服务程序在下一条指令（803）开始执行之前，上下文切换和返回（830,832）之前完成指令。执行一系列操作的其他指令也可以以类似的方式中断。

4. 发明授权

US06760829B2 MMU descriptor having big/little endian bit to control the transfer data between devices 有权
标题翻译： MMU描述符具有大/小端位以控制设备之间的传输数据
公开(公告)号：US06760829B2
公开(公告)日：2004-07-06
申请号：US09932807
申请日：2001-08-17
申请人： Serge Lasserre , Gerard Chauvel , Dominique D'Inverno
发明人： Serge Lasserre , Gerard Chauvel , Dominique D'Inverno
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F12/0292 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system is provided with a memory (506) shared by several initiator resources (540-550), wherein a portion of the initiator resources are big endian and another portion of the initiator resources are little endian. The memory is segregated into a set of regions by a memory management unit (MMU) (500-510) and an endianism attribute bit is defined for each region. For each memory request to the memory, the endianism attribute bit for the selected region is provided by the MMU. Each memory transaction request is completed in accordance with the endianism attribute of the selected region. Depending on the capability of a given initiator resource, the memory request address is adjusted to agree with the endianism attribute of the selected region, or an access fault is generated (530) if the endianism of the initiating resource does not match the endianism attribute of the selected memory region. A resource identification value (R-ID) provided by each of the initiator resources is used to identify the endianism of each of the initiator resources.
摘要翻译：数字系统具有由几个发起者资源（540-550）共享的存储器（506），其中一部分发起者资源是大端，另一部分发起者资源是小端。存储器通过存储器管理单元（MMU）（500-510）分离成一组区域，并且为每个区域定义一个endianistic属性位。对于存储器的每个存储器请求，MMU提供所选区域的endianistic属性位。每个存储器事务请求都是根据所选区域的endianism属性完成的。根据给定的启动器资源的能力，调整存储器请求地址以与所选区域的endianism属性一致，或者如果启动资源的endianism不匹配于endianism属性，则生成访问故障（530）所选存储区域。由每个启动器资源提供的资源标识值（R-ID）用于识别每个发起者资源的端点。

5. 发明授权

US06754781B2 Cache with DMA and dirty bits 有权
标题翻译：缓存与DMA和脏位
公开(公告)号：US06754781B2
公开(公告)日：2004-06-22
申请号：US09932643
申请日：2001-08-17
申请人： Gerard Chauvel , Serge Lasserre
发明人： Gerard Chauvel , Serge Lasserre
IPC分类号： G06F1208
CPC分类号： G06F9/30043 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F12/0292 , G06F12/0804 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (506(n). Validity circuitry (VI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Dirty bit circuitry (DI) is connected to the memory circuit for indicating if data within the cache is incoherent with a secondary back-up memory. DMA circuitry can transfer (1652) blocks of data/instructions (1660) between the cache and a secondary memory (1602). A transfer mode circuit (1681) controls how DMA operations are affected by the dirty bits. If the transfer mode circuit is in a first mode, a DMA operation transfers only segments (1661) indicated as dirty (1685). If the transfer mode circuit is in a second mode, a DMA operation transfers and entire block of data (1660) without regard to dirty indicators (1686). DMA transfers from the cache to secondary memory are thereby configured to be responsive to the dirty bits. A dirty bit mode circuit (1680) controls how DMA transfers affect the dirty bits. When the mode circuit is in a first mode, DMA transfers set the affected dirty bits to a clean state. When the dirty bit mode circuitry is in an alternate mode, DMA transfers set the affected dirty bits to a dirty state. A cache clean operation will thus copy data provided by a DMA transfer and indicated as dirty into backup secondary memory.
摘要翻译：提供了一种数字系统和操作方法，其中数字系统具有至少一个具有相关联的多段高速缓冲存储器电路（506（n））的处理器，有效电路（VI）连接到存储器电路，并且可操作以指示多个段的每个段是否保存有效数据，脏位电路（DI）连接到存储器电路，用于指示高速缓存内的数据是否与辅助备份存储器不相干，DMA电路可以传输（1652）块传输模式电路（1681）控制DMA操作如何受脏位的影响，如果传输模式电路处于第一模式，DMA操作（1660）只传输指示为脏的段（1661）（1685），如果传输模式电路处于第二模式，则DMA操作传输和整个数据块（1660），而不考虑脏指示器（1686）。到二级记忆从而被配置为响应于脏位。脏位模式电路（1680）控制DMA传输如何影响脏位。当模式电路处于第一模式时，DMA将受影响的脏位设置为干净状态。当脏位模式电路处于交替模式时，DMA传送将受影响的脏位设置为脏状态。因此，高速缓存清理操作将复制由DMA传输提供的数据，并将其标记为脏到备用辅助存储器中。

6. 发明授权

US06728838B2 Cache operation based on range of addresses 有权
标题翻译：基于地址范围的缓存操作
公开(公告)号：US06728838B2
公开(公告)日：2004-04-27
申请号：US09932634
申请日：2001-08-17
申请人： Gerard Chauvel , Serge Lasserre
发明人： Gerard Chauvel , Serge Lasserre
IPC分类号： G06F1212
CPC分类号： G06F1/329 , G06F1/206 , G06F1/3203 , G06F9/30047 , G06F12/0292 , G06F12/0804 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (1806(n). Validity circuitry (VI) and dirty bit circuitry (DI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Block circuitry (700, 702) is connected to the set of valid bits and dirty bits and is operable to invalidate a selected range of lines in response to a directive from the first processor. The block circuitry has a start register (700) and an end register (702) each separately loadable by the processor. The block circuitry can invalidate either a single line or a block of lines in response to an operation command from the processor, depending on whether the end register is loaded or not. Likewise, the block circuitry can clean a single line or a block of lines in response to an operation command from the processor.
摘要翻译：提供了一种数字系统和操作方法，其中数字系统具有至少一个处理器，具有相关联的多段高速缓冲存储器电路（1806（n）），有效电路（VI）和脏位电路（DI）连接到存储器电路并且可操作以指示多个段中的每个段是否保存有效数据。块电路（700,702）连接到该组有效位和脏位，并且可操作以使响应中的所选行范围无效块电路具有开始寄存器（700）和结束寄存器（702），每个开关寄存器（700）和终端寄存器（702）都可以由处理器分别加载。块电路可以响应于第一处理器使单行或一组线路无效来自处理器的操作命令，取决于结束寄存器是否被加载。同样地，块电路可以响应于来自处理器的操作命令来清除单行或一行线。

7. 发明授权

US06430664B1 Digital signal processor with direct and virtual addressing 有权
标题翻译：具有直接和虚拟寻址功能的数字信号处理器
公开(公告)号：US06430664B1
公开(公告)日：2002-08-06
申请号：US09434606
申请日：1999-11-05
申请人： Gérard Chauvel , Serge Lasserre , Dominique Benoît Jacques d'Inverno
发明人： Gérard Chauvel , Serge Lasserre , Dominique Benoît Jacques d'Inverno
IPC分类号： G06F1200
CPC分类号： G06F12/1027
摘要： A DSP (10) accesses internal memory using physical addresses and has a internal MMU (19) which allows the DSP (10) to work with a large virtual address space mapped to an external memory (20). The MMU (19) performs the translation between a virtual address and the physical address associated with the external memory (20). The MMU (19) includes a translation lookaside buffer (28) and walking table logic (32) for translating virtual addresses to physical addresses.
摘要翻译： DSP（10）使用物理地址访问内部存储器并且具有内部MMU（19），其允许DSP（10）处理映射到外部存储器（20）的大的虚拟地址空间。 MMU（19）执行虚拟地址与与外部存储器（20）相关联的物理地址之间的转换。 MMU（19）包括翻译后备缓冲器（28）和用于将虚拟地址转换为物理地址的步行表逻辑（32）。

8. 发明授权

US06310657B1 Real time window address calculation for on-screen display 有权
标题翻译：屏幕显示实时窗口地址计算
公开(公告)号：US06310657B1
公开(公告)日：2001-10-30
申请号：US09679000
申请日：2000-10-04
申请人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
发明人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
IPC分类号： H04N550
CPC分类号： H04N21/8166 , G09G5/14 , G09G5/395 , G09G2340/04 , G09G2340/125 , G09G2360/02 , H04L29/06 , H04L69/22 , H04N5/44 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N7/0882 , H04N11/20 , H04N19/42 , H04N19/61 , H04N21/42204 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/42653 , H04N21/4305 , H04N21/431 , H04N21/4316 , H04N21/434 , H04N21/43632 , H04N21/439 , H04N21/44 , H04N21/443 , H04N21/47
摘要： An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.
摘要翻译：其中CPU在工作存储器空间中生成窗口的屏幕显示系统还提供对工作存储器空间中的窗口地址的实时计算。这可以消除对单独的帧缓冲存储器的需要。

9. 发明授权

US07757067B2 Pre-decoding bytecode prefixes selectively incrementing stack machine program counter 有权
标题翻译：预解码字节码前缀选择性地递增堆栈机器程序计数器
公开(公告)号：US07757067B2
公开(公告)日：2010-07-13
申请号：US10632222
申请日：2003-07-31
申请人： Gerard Chauvel , Serge Lasserre , Maija Kuusela
发明人： Gerard Chauvel , Serge Lasserre , Maija Kuusela
IPC分类号： G06F9/30 , G06F9/40
CPC分类号： G06F9/30149 , G06F9/30076 , G06F9/30181 , G06F9/30185 , G06F9/382 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecodes in parallel with the decoder decoding a current instruction. The pre-decoder determines if a subsequent instruction contains a prefix. If a prefix is detected in at least one of the five Bytecodes, a program counter skips the prefix and changes the behavior of the decoder during the decoding of the subsequent instruction.
摘要翻译：包括耦合到预解码器的解码器的处理器（例如，协处理器），其中解码器与预解码器并行地解码当前指令，以对后续指令进行解码。特别地，预解码器与解码器解码当前指令并行地检查至少五个字节码。预解码器确定后续指令是否包含前缀。如果在五个字节码中的至少一个中检测到前缀，则程序计数器跳过前缀，并且在后续指令的解码期间改变解码器的行为。

10. 发明授权

US07496930B2 Accessing device driver memory in programming language representation 有权
标题翻译：以编程语言表示访问设备驱动程序内存
公开(公告)号：US07496930B2
公开(公告)日：2009-02-24
申请号：US10831575
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F13/00
CPC分类号： G09G5/39 , G06F3/14 , G09G5/393
摘要： In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the application software to manage the device and also comprises instructions that map the application data structure to a memory associated with the device without the use of a device driver. In other embodiments, a method comprises initializing an application data structure to manage a hardware device and mapping the application data structure to a memory associated with the hardware device without the use of a device driver. The application data structure may store a single dimensional data structure or a multi-dimensional data structure. In some embodiments, the device being managed by the application software may comprise a display and the application software may comprise Java code.
摘要翻译：在一些实施例中，存储介质包括执行一个或多个操作并直接管理设备的应用软件。应用软件包括初始化应用软件可用于管理设备的应用数据结构（例如，对象或阵列）的指令，还包括将应用数据结构映射到与设备相关联的存储器而不使用设备驱动。在其他实施例中，一种方法包括初始化应用数据结构以管理硬件设备，并将应用数据结构映射到与硬件设备相关联的存储器，而不使用设备驱动程序。应用数据结构可以存储单维数据结构或多维数据结构。在一些实施例中，由应用软件管理的设备可以包括显示器，并且应用软件可以包括Java代码。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式