专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08604898B2 Vertical integrated circuit switches, design structure and methods of fabricating same 有权
标题翻译：垂直集成电路开关，设计结构及其制造方法
公开(公告)号：US08604898B2
公开(公告)日：2013-12-10
申请号：US12426561
申请日：2009-04-20
申请人： Felix P. Anderson , Edward C. Cooney, III , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , Edward C. Cooney, III , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01H51/22
CPC分类号： H01H59/0009 , H01L2924/0002 , H01L2924/00
摘要： Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.
摘要翻译：本文提供垂直集成MEMS开关，制造这种垂直开关的设计结构和方法。制造MEMS开关的方法包括在晶片中形成至少两个垂直延伸的通孔，并用金属填充至少两个垂直延伸的通孔以形成至少两个垂直延伸的导线。该方法还包括从底侧打开晶片中的空隙，使得垂直延伸的线中的至少一个可在空隙内移动。

2. 发明申请

US20130133919A1 TOP CORNER ROUNDING OF DAMASCENE WIRE FOR INSULATOR CRACK SUPPRESSION 失效
标题翻译：用于绝缘体破裂阻抗的绝缘线的顶角
公开(公告)号：US20130133919A1
公开(公告)日：2013-05-30
申请号：US13304772
申请日：2011-11-28
申请人： Gregory S. Chrisman , Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Thomas L. McDevitt , Eva A. Shah
发明人： Gregory S. Chrisman , Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Thomas L. McDevitt , Eva A. Shah
IPC分类号： H01B3/10 , H01B7/00 , H01B19/00
CPC分类号： H01L23/562 , H01L21/7684 , H01L21/76883 , H01L23/5227 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire.
摘要翻译：一种用于制造提供在上表面具有第一高度的金属线的结构的结构和方法。围绕所述金属线的绝缘材料被蚀刻到所述上表面的所述第一高度以下的第二高度。在蚀刻所述绝缘材料之后，来自所述上表面的金属线被平坦化以从所述金属线的横向边缘部分去除足够的材料，使得所述侧边缘部分的高度等于围绕所述绝缘材料的所述绝缘材料的所述第二高度金属丝。

3. 发明申请

US20120018832A1 METHODS, STRUCTURES, AND DESIGN STRUCTURES FOR IMPROVED ADHESION OF PROTECTIVE LAYERS OF IMAGER MICROLENS STRUCTURES 有权
标题翻译：改善胶片微结构保护层粘结的方法，结构和设计结构
公开(公告)号：US20120018832A1
公开(公告)日：2012-01-26
申请号：US12841750
申请日：2010-07-22
申请人： Edward C. COONEY, III , Jeffrey P. GAMBINO , Robert K. LEIDY , Charles F. MUSANTE , John G. TWOMBLY
发明人： Edward C. COONEY, III , Jeffrey P. GAMBINO , Robert K. LEIDY , Charles F. MUSANTE , John G. TWOMBLY
IPC分类号： H01L31/0232 , G06F17/50 , H01L21/30 , H01L31/18
CPC分类号： H01L31/02325 , C23C16/02 , C23C16/0272 , C23C16/402 , C23C16/505 , G06F17/5045 , H01L27/14627 , H01L27/14685
摘要： Methods, structures, and design structures for improved adhesion of protective layers of imager microlens structures are disclosed. A method of fabricating a semiconductor structure includes forming an interfacial region between a microlens and a protective oxide layer. The interfacial region has a lower concentration of oxygen than the protective oxide layer.
摘要翻译：公开了用于改善成像器微透镜结构保护层附着力的方法，结构和设计结构。制造半导体结构的方法包括在微透镜和保护氧化物层之间形成界面区域。界面区域的氧浓度低于保护氧化物层。

4. 发明授权

US07892940B2 Device and methodology for reducing effective dielectric constant in semiconductor devices 有权
标题翻译：用于降低半导体器件中有效介电常数的器件和方法
公开(公告)号：US07892940B2
公开(公告)日：2011-02-22
申请号：US11851123
申请日：2007-09-06
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.
摘要翻译：一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻特征跨越至少一个互连的侧壁。

5. 发明授权

US07541679B2 Exposed pore sealing post patterning 有权
标题翻译：曝露孔密封柱图案化
公开(公告)号：US07541679B2
公开(公告)日：2009-06-02
申请号：US11247818
申请日：2005-10-11
申请人： Edward C Cooney, III , John A Fitzsimmons , Jeffrey P Gambino , Stephen E Luce , Thomas L McDevitt , Lee M Nicholson , Anthony K Stamper
发明人： Edward C Cooney, III , John A Fitzsimmons , Jeffrey P Gambino , Stephen E Luce , Thomas L McDevitt , Lee M Nicholson , Anthony K Stamper
IPC分类号： H01L23/48
CPC分类号： H01L21/76831 , H01L21/02107 , H01L21/02203 , H01L21/02337 , H01L21/0234 , H01L21/02362 , H01L21/3105 , H01L21/31116 , H01L21/31695 , H01L21/76802 , H01L21/76807 , H01L21/76826 , H01L21/76843 , H01L21/76844 , H01L21/76868
摘要： Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed-pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant Into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.
摘要翻译：具有闭孔层的方法和结构，用于封闭图案化的多孔低k电介质层中的暴露孔，以及可选地在低k电介质上的反应性衬垫。第一反应物被吸收或保留在图案化介电层中的暴露孔中，然后将第二反应物引入开口中，使得其进入暴露的孔，同时第一反应物分子同时脱气。第二反应物与暴露孔的口部区域处的脱气的第一反应物分子原位反应，以形成穿过暴露孔的口部区域的孔闭合层，同时保留每个孔隙的一部分以保持其孔的特性和性质多孔低k电介质层。任选地，第一反应物可以被吸附到低k电介质上，使得当将第二反应物引入到图案化的电介质开口中时，还在低k电介质上形成反应性衬垫。

6. 发明授权

US07393777B2 Sacrificial metal spacer damascene process 有权
标题翻译：牺牲金属间隔镶嵌工艺
公开(公告)号：US07393777B2
公开(公告)日：2008-07-01
申请号：US10984439
申请日：2004-11-09
申请人： Edward C. Cooney, III , Robert M. Geffken , Anthony K. Stamper
发明人： Edward C. Cooney, III , Robert M. Geffken , Anthony K. Stamper
IPC分类号： H01L21/4763 , H01L21/311
CPC分类号： H01L21/76844 , H01L21/76811 , H01L21/76813
摘要： A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias. Moreover, the step of depositing comprises cleaning the vias and troughs, optionally performing a reactive ion etching or argon sputter cleaning, depositing a plurality of metal layers over the vias and troughs, and depositing copper in the vias and troughs.
摘要翻译：用于双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上方形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽，从而产生牺牲钨在槽中的侧壁间隔物，图案化叠层绝缘体堆叠，去除牺牲侧壁间隔物，在图案化的层压绝缘体堆叠中形成通孔，以及将金属衬垫和导电材料沉积到通孔和槽中，其中层压绝缘体堆叠包括介电层还包含氧化物和聚亚芳基。沉积步骤防止层压的绝缘体叠层溅射到通孔中。此外，沉积步骤包括清洁通孔和槽，可选地执行反应离子蚀刻或氩溅射清洗，在通孔和槽上沉积多个金属层，以及在通孔和槽中沉积铜。

7. 发明授权

US06846741B2 Sacrificial metal spacer damascene process 失效
标题翻译：牺牲金属间隔镶嵌工艺
公开(公告)号：US06846741B2
公开(公告)日：2005-01-25
申请号：US10202134
申请日：2002-07-24
申请人： Edward C. Cooney, III , Robert M. Geffken , Anthony K. Stamper
发明人： Edward C. Cooney, III , Robert M. Geffken , Anthony K. Stamper
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76811 , H01L21/76813
摘要： A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias. Moreover, the step of depositing comprises cleaning the vias and troughs, optionally performing a reactive ion etching or argon sputter cleaning, depositing a plurality of metal layers over the vias and troughs, and depositing copper in the vias and troughs.
摘要翻译：用于双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上方形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽，从而产生牺牲钨在槽中的侧壁间隔物，图案化叠层绝缘体堆叠，去除牺牲侧壁间隔物，在图案化的层压绝缘体堆叠中形成通孔，以及将金属衬垫和导电材料沉积到通孔和槽中，其中层压绝缘体堆叠包括介电层还包含氧化物和聚亚芳基。沉积步骤防止层压的绝缘体叠层溅射到通孔中。此外，沉积步骤包括清洁通孔和槽，可选地执行反应离子蚀刻或氩溅射清洗，在通孔和槽上沉积多个金属层，以及在通孔和槽中沉积铜。

8. 发明授权

US06674168B1 Single and multilevel rework 失效
标题翻译：单层和多层返工
公开(公告)号：US06674168B1
公开(公告)日：2004-01-06
申请号：US10248452
申请日：2003-01-21
申请人： Edward C. Cooney, III , Robert M Geffken , Vincent J McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
发明人： Edward C. Cooney, III , Robert M Geffken , Vincent J McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
IPC分类号： H01L2100
CPC分类号： H01L21/76808 , H01L21/76801 , H01L21/76807 , H01L21/76892 , H01L23/525 , H01L23/5329 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.
摘要翻译：一种重新加工BEOL（处理线的后端）金刚石冶金的金属化水平的方法包括在衬底上形成多个BEOL金属化水平，在BEOL金属化水平中形成线和通孔部分，选择性地去除BEOL金属化中的至少一个以暴露线路和通孔部分，并且用至少一个新的BEOL金属化水平替换去除的BEOL金属化水平，其中BEOL金属化水平包括第一介电层和第二介电层，并且其中第一介电层包括下部介电常数材料比第二介电层。

9. 发明授权

US08969195B2 Methods of manufacturing semiconductor devices and a semiconductor structure 有权
标题翻译：制造半导体器件和半导体结构的方法
公开(公告)号：US08969195B2
公开(公告)日：2015-03-03
申请号：US12035449
申请日：2008-02-22
申请人： Felix P. Anderson , Steven P. Barkyoumb , Edward C. Cooney, III , Thomas L. McDevitt , William J. Murphy , David C. Strippe
发明人： Felix P. Anderson , Steven P. Barkyoumb , Edward C. Cooney, III , Thomas L. McDevitt , William J. Murphy , David C. Strippe
IPC分类号： H01L21/44 , H01L21/285 , C23C14/02 , C23C14/06 , H01L21/768
CPC分类号： H01L23/53209 , C23C14/02 , C23C14/0641 , H01L21/2855 , H01L21/76843 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.
摘要翻译：提供了用于改善膜对半导体晶片和半导体结构的附着力的方法。通过实施本发明的方法，可以在晶片制造工艺期间显着抑制缺陷产生，例如减少颗粒产生。更具体地，所描述的工艺通过有效地增加TaN膜在晶片上的粘合性能，显着地减少了晶片的边缘或边缘（斜面）对TaN膜的剥落。在阻挡层制造过程中，相对于总钽加氮化物将氮化物的摩尔百分数提高到25％或更大的方法。

10. 发明授权

US08765595B2 Thick on-chip high-performance wiring structures 有权
标题翻译：厚片上高性能布线结构
公开(公告)号：US08765595B2
公开(公告)日：2014-07-01
申请号：US13345120
申请日：2012-01-06
申请人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , Xiao H. Liu
发明人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , Xiao H. Liu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5227 , H01L21/76883 , H01L23/5283 , H01L23/5329 , H01L23/53295 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.
摘要翻译： BEOL布线结构的制造方法，BEOL布线结构以及BEOL布线结构的设计结构。 BEOL布线可以通过在电介质层中形成第一布线并在无氧气氛中退火第一布线来制造。在第一线退火之后，形成与第一线垂直对准的第二线。形成由诸如聚酰亚胺的有机材料组成的最终钝化层，其覆盖第二线的整个侧壁。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式