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1. 发明申请

US20130068617A1 CHARGED ENTITIES AS LOCOMOTIVE TO CONTROL MOTION OF POLYMERS THROUGH A NANOCHANNEL 有权
公开(公告)号：US20130068617A1
公开(公告)日：2013-03-21
申请号：US13234276
申请日：2011-09-16
申请人： Stefan Harrer , Binquan Luan , Glenn J. Martyna , Hongbo Peng , Stanislav Polonsky , Stephen M. Rossnagel , Ajay K. Royyuru , Gustavo A. Stolovitzky , George F. Walker
发明人： Stefan Harrer , Binquan Luan , Glenn J. Martyna , Hongbo Peng , Stanislav Polonsky , Stephen M. Rossnagel , Ajay K. Royyuru , Gustavo A. Stolovitzky , George F. Walker
IPC分类号： C25B7/00 , C25B15/00 , B82Y99/00
CPC分类号： B82Y15/00 , C12Q1/6869 , C12Q2565/631
摘要： A technique for controlling the motion of one or more charged entities linked to a polymer through a nanochannel is provided. A first reservoir and a second reservoir are connected by the nanochannel. An array of electrodes is positioned along the nanochannel, where fluid fills the first reservoir, the second reservoir, and the nanochannel. A first electrode is in the first reservoir and a second electrode is in the second reservoir. The first and second electrodes are configured to direct the one or more charged entities linked to the polymer into the nanochannel. An array of electrodes is configured to trap the one or more charged entities in the nanochannel responsive to being controlled for trapping. The array of electrodes is configured to move the one or more charged entities along the nanochannel responsive to being controlled for moving.

2. 发明申请

US20130001082A1 DNA SEQUENCING USING MULTIPLE METAL LAYER STRUCTURE WITH ORGANIC COATINGS FORMING TRANSIENT BONDING TO DNA BASES 有权
标题翻译：使用多种金属层结构的DNA序列与有机涂层形成瞬态结合到DNA基础
公开(公告)号：US20130001082A1
公开(公告)日：2013-01-03
申请号：US13607070
申请日：2012-09-07
申请人： Ali Afzali-Ardakani , Stefan Harrer , Binquan Luan , Glenn J. Martyna , Hongbo Peng , Stephen M. Rossnagel , Gustavo A. Stolovitzky , Philip S. Waggoner , George F. Walker
发明人： Ali Afzali-Ardakani , Stefan Harrer , Binquan Luan , Glenn J. Martyna , Hongbo Peng , Stephen M. Rossnagel , Gustavo A. Stolovitzky , Philip S. Waggoner , George F. Walker
IPC分类号： G01N27/447 , B82Y30/00
CPC分类号： G01N33/48721 , C12Q1/6869 , C12Q2563/116 , C12Q2563/157 , C12Q2565/607 , C12Q2565/631
摘要： A technique for nanodevice is provided. A reservoir is filled with an ionic fluid. A membrane separates the reservoir, and the membrane includes electrode layers separated by insulating layers in which the electrode layers have an organic coating. A nanopore is formed through the membrane, and the organic coating on the electrode layers forms transient bonds to a base of a molecule in the nanopore. When a first voltage is applied to the electrode layers a tunneling current is generated by the base in the nanopore, and the tunneling current travels through the transient bonds formed to the base to be measured as a current signature for distinguishing the base.
摘要翻译：提供了一种纳米设备技术。储存器充满离子流体。膜分离储存器，并且膜包括由绝缘层分离的电极层，其中电极层具有有机涂层。通过膜形成纳米孔，并且电极层上的有机涂层与纳米孔中分子的碱基形成瞬态键。当第一电压施加到电极层时，通过纳米孔中的基底产生隧道电流，并且隧道电流通过形成到待测量的基极的瞬态键作为用于区分基极的电流签名传播。

3. 发明申请

US20090269286A1 SYSTEM AND METHOD FOR AUTHENTICATING PHARMACEUTICALS USING INTERNALLY LOCATED HYDROSCOPIC GELS WITH INDICIA 有权
标题翻译：用INDIIA内部定位的胶体凝胶来确认药物的系统和方法
公开(公告)号：US20090269286A1
公开(公告)日：2009-10-29
申请号：US12111503
申请日：2008-04-29
申请人： George F. Walker
发明人： George F. Walker
IPC分类号： A61K9/44
CPC分类号： A61K9/2072 , A61J3/007 , A61J2200/20 , A61J2205/10 , A61J2205/20 , A61J2205/40 , A61J2205/50
摘要： The invention is an article of manufacture, comprising an identifying marker disposed in a pharmaceutical product. The pharmaceutical product may be selected from the group consisting of a pharmaceutical liquid, a pill, a tablet, a caplet, and a capsule. The identifying marker may be a hydroscopic medium having an indicia imprinted thereon or within, where the marker expands volumetrically when contacted with a liquid.
摘要翻译：本发明是一种制品，其包括设置在药品中的识别标记。药物产品可以选自药物液体，丸剂，片剂，囊片和胶囊。识别标记物可以是具有印记在其上或内部的标记的吸湿介质，其中当与液体接触时，标记物在体积上膨胀。

4. 发明授权

US07273806B2 Forming of high aspect ratio conductive structure using injection molded solder 有权
标题翻译：使用注塑焊料形成高纵横比导电结构
公开(公告)号：US07273806B2
公开(公告)日：2007-09-25
申请号：US10905013
申请日：2004-12-09
申请人： Robert A. Groves , Peter A. Gruber , Kevin S. Petrarca , Richard P. Volant , George F. Walker
发明人： Robert A. Groves , Peter A. Gruber , Kevin S. Petrarca , Richard P. Volant , George F. Walker
IPC分类号： H01L21/44
CPC分类号： H05K3/3468 , G01R1/07314 , G01R3/00 , H01L21/4853 , H01L21/6835 , H01L24/11 , H01L2224/13099 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01018 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/01058 , H01L2924/01066 , H01L2924/01067 , H01L2924/01068 , H01L2924/01075 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/19041 , H01L2924/19042 , H05K3/325 , H05K2201/09745 , H05K2201/10734 , H05K2203/0113 , H05K2203/0338 , H05K2203/128 , H05K2203/162 , H05K2203/167 , H01L2224/0401
摘要： Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.
摘要翻译：公开了在封装之前在基板上形成导电结构的方法和根据该方法生成的测试探针结构。导电结构包括通过注射成型的焊料形成的高纵横比结构。本发明可以应用于在典型的BEOL之后以及在封装之前在常规半导体衬底上形成无源元件和互连。该方法可以为导电结构提供更好的电迁移特性，较低的电阻率和更高的Q因子。此外，该方法可以向后兼容并可定制。

5. 发明授权

US07252514B2 High density space transformer and method of fabricating same 失效
标题翻译：高密度空间变压器及其制造方法
公开(公告)号：US07252514B2
公开(公告)日：2007-08-07
申请号：US10931428
申请日：2004-09-02
申请人： Samuel R. McKnight , George F. Walker
发明人： Samuel R. McKnight , George F. Walker
IPC分类号： H01R12/00 , H05K1/00
CPC分类号： H01R9/0515 , G01R1/06772 , G01R1/07378
摘要： A method for forming a space transformer (and a space transformer formed by the method) having a first plate and a second plate, the plates being separated by a frame, and electrical connectors for providing electrical connections between electrical contacts which are relatively closely spaced on the first plate and relatively more widely spaced on the second plate. The method comprises attaching first ends of wires to first electrically conductive regions on the first plate; forming insulating layers over the wires; forming electrically conductive coverings over the insulating layers; and connecting second ends of the wires to second electrically conductive regions on the second plate.
摘要翻译：一种用于形成具有第一板和第二板的空间变压器（和由该方法形成的空间变压器）的方法，所述板由框架分隔开，并且电连接器用于在电触点之间提供电连接，所述电触点相对紧密地间隔开第一板并且在第二板上相对更宽的间隔。该方法包括将导线的第一端附接到第一板上的第一导电区域; 在导线上形成绝缘层; 在绝缘层上形成导电覆盖物; 并且将所述导线的第二端连接到所述第二板上的第二导电区域。

6. 发明授权

US06656750B1 Method for testing chips on flat solder bumps 失效
标题翻译：在平坦焊料凸块上测试芯片的方法
公开(公告)号：US06656750B1
公开(公告)日：2003-12-02
申请号：US09301889
申请日：1999-04-29
申请人： Madhav Datta , Peter A. Gruber , Judith M. Rubino , Carlos J. Sambucetti , George F. Walker
发明人： Madhav Datta , Peter A. Gruber , Judith M. Rubino , Carlos J. Sambucetti , George F. Walker
IPC分类号： G01R3126
CPC分类号： H01L24/13 , B23K1/0016 , B23K1/20 , B23K2101/36 , G01R31/2886 , H01L22/00 , H01L24/11 , H01L24/14 , H01L2224/0401 , H01L2224/0603 , H01L2224/1148 , H01L2224/1184 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/1403 , H01L2224/14051 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01039 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H05K3/3436 , H01L2924/00014
摘要： A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than ½ of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders. When the MSS method is used for planting the bumps, solder bumps are transferred onto the wafer surface in a substantially flattened hemi-spherical shape.
摘要翻译：公开了一种在平坦焊料凸块上测试集成电路芯片的方法以及配备有平坦焊料凸块的IC芯片。在该方法中，首先提供具有多个接合焊盘和多个平坦焊料凸块的IC芯片，其中每个焊料凸块在多个焊盘上具有小于其直径的1/2的高度。因此，探针线可以容易地用于接触焊料凸块上的增加的目标区域，以建立与测试电路的电连接。探针可以容易地进行，凸块的所有Z高度基本相等。焊料凸块的高度可以通过平面化处理来适当地控制，其中软焊料凸块被平面表面压缩，或者通过用于形成焊料凸块的MSS或电镀工艺在原位模具中形成焊料凸块呈短圆柱形。当使用MSS方法种植凸块时，焊料凸块以大致平坦的半球形转移到晶片表面上。

7. 发明授权

US06534863B2 Common ball-limiting metallurgy for I/O sites 有权
公开(公告)号：US06534863B2
公开(公告)日：2003-03-18
申请号：US09781121
申请日：2001-02-09
申请人： George F. Walker , Ronald D. Goldblatt , Peter A. Gruber , Raymond R. Horton , Kevin S. Petrarca , Richard P. Volant , Tien-Jen Cheng
发明人： George F. Walker , Ronald D. Goldblatt , Peter A. Gruber , Raymond R. Horton , Kevin S. Petrarca , Richard P. Volant , Tien-Jen Cheng
IPC分类号： H01L2348
CPC分类号： H01L24/48 , H01L21/76865 , H01L21/76873 , H01L21/76879 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/85 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05083 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05169 , H01L2224/05181 , H01L2224/05556 , H01L2224/05572 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/11912 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/13116 , H01L2224/16 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85207 , H01L2924/0001 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00 , H01L2224/05552 , H01L2924/00015 , H01L2924/00012
摘要： A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

8. 发明授权

US06339024B1 Reinforced integrated circuits 失效
标题翻译：强化集成电路
公开(公告)号：US06339024B1
公开(公告)日：2002-01-15
申请号：US09605728
申请日：2000-06-28
申请人： Kevin S. Petrarca , John E. Heidenreich, III , Judith M. Rubino , Carlos J. Sambucetti , Richard P. Volant , George F. Walker
发明人： Kevin S. Petrarca , John E. Heidenreich, III , Judith M. Rubino , Carlos J. Sambucetti , Richard P. Volant , George F. Walker
IPC分类号： H01L2044
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/14
摘要： A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.
摘要翻译：一种制造集成电路的方法，其中提供具有大于或等于1.5μm厚度的集成电路的最上半导体层中的导电结构。导电结构的厚度足够大，以有效地保护最高半导体层下面的任何层免受来自压力（例如由测试探针施加的压力）的损害。在优选的实施方案中，传统的铝TD匀染被丢弃，有利于沉积在增厚的导电层上的金。

9. 发明授权

US5633047A Electronic devices having metallurgies containing copper-semiconductor compounds 失效
标题翻译：具有包含铜半导体化合物的冶金的电子器件
公开(公告)号：US5633047A
公开(公告)日：1997-05-27
申请号：US449196
申请日：1995-05-24
申请人： Michael J. Brady , Curtis E. Farrell , Sung K. Kang , Jeffrey R. Marino , Donald J. Mikalsen , Paul A. Moskowitz , Eugene J. O'Sullivan , Terrence R. O'Toole , Sampath Purushothaman , Sheldon C. Rieley , George F. Walker
发明人： Michael J. Brady , Curtis E. Farrell , Sung K. Kang , Jeffrey R. Marino , Donald J. Mikalsen , Paul A. Moskowitz , Eugene J. O'Sullivan , Terrence R. O'Toole , Sampath Purushothaman , Sheldon C. Rieley , George F. Walker
IPC分类号： C23C18/50 , C25D3/54 , H01L23/495 , H01L23/532 , B05D1/18
CPC分类号： H01L24/12 , C23C18/50 , C25D3/54 , H01L23/4951 , H01L23/53271 , H01L24/05 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05644 , H01L2224/05647 , H01L2224/13099 , H01L2224/32014 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/4847 , H01L2224/48644 , H01L2224/48647 , H01L2224/48747 , H01L2224/48844 , H01L2224/48847 , H01L2224/73215 , H01L2224/85201 , H01L2224/85205 , H01L2224/85214 , H01L24/45 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12042 , H01L2924/14 , H01L2924/15747 , H01L2924/15787 , H01L2924/181
摘要： Silicon and germanium containing materials are used at surface of conductors in electronic devices. Solder can be fluxlessly bonded and wires can be wire bonded to these surfaces. These material are used as a surface coating for lead frames for packaging integrated circuit chips. These materials can be decal transferred onto conductor surfaces or electrolessly or electrolytically disposed thereon.
摘要翻译：在电子设备中的导体的表面使用含锗和锗的材料。焊料可无焊接，电线可以与这些表面引线接合。这些材料用作用于封装集成电路芯片的引线框架的表面涂层。这些材料可以贴花地转移到导体表面上，或者无电解或电解地放置在其上。

10. 发明授权

US5600257A Semiconductor wafer test and burn-in 失效
标题翻译：半导体晶圆测试和老化
公开(公告)号：US5600257A
公开(公告)日：1997-02-04
申请号：US513057
申请日：1995-08-09
申请人： James M. Leas , Robert W. Koss , George F. Walker , Charles H. Perry , Jody J. Van Horn
发明人： James M. Leas , Robert W. Koss , George F. Walker , Charles H. Perry , Jody J. Van Horn
IPC分类号： G01R1/06 , G01R1/073 , G01R31/28 , H01L21/66 , G01R1/02
CPC分类号： G01R1/07385 , G01R1/07314 , G01R31/2889 , G01R31/2863 , G01R31/2879 , G01R31/2886
摘要： An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.
摘要翻译：用于在产品晶片上的所有集成电路芯片中同时测试或燃烧的装置和方法。该装置包括具有测试芯片的玻璃陶瓷载体和用于连接到产品晶片上的大量芯片的焊盘的装置。测试芯片上的电压调节器提供电源和产品芯片上的电源接口之间的接口，每个产品芯片至少有一个电压调节器。电压调节器向产品芯片提供指定的Vdd电压，由此Vdd电压基本上与产品芯片所消耗的电流无关。电压调节器或其他电子装置将电流限制在任何产品芯片上。电压调节器电路可以是门控和可变的，并且其可以具有延伸到产品芯片的传感器线路。测试芯片还可以提供测试功能，例如测试模式和用于存储测试结果的寄存器。

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