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1. 发明申请

US20050182811A1 Method and apparatus supporting non-additive calculations in graphics accelerators and digital signal processors 失效
标题翻译：在图形加速器和数字信号处理器中支持非加法计算的方法和装置
公开(公告)号：US20050182811A1
公开(公告)日：2005-08-18
申请号：US11036538
申请日：2005-01-13
申请人： Earle Jennings , George Landers , Robert Spence
发明人： Earle Jennings , George Landers , Robert Spence
IPC分类号： G06F1/03 , G06F7/48 , G06F7/52 , G06F7/523 , G06F7/57 , G06F7/38
CPC分类号： G06F7/57 , G06F1/0307 , G06F7/4806 , G06F7/5235
摘要： A method and apparatus receiving number and using instruction to create resulting number approximating one of square root, reciprocal, or reciprocal square root of number. The resulting number as a product of that process. Using resulting number in a graphics accelerator. Apparatus preferably includes log-calculator, log-arithmetic-unit, and exponential-calculator. At least one of log-calculator and exponential-calculator include implementation non-linear calculator. The non-linear calculators may use at least one of mid-band-filter, outlier-removal-circuit. The invention includes making arithmetic circuit, log-calculator, log-arithmetic-unit and exponential-calculator. The arithmetic circuit, log-calculator, log-arithmetic-unit and exponential-calculator as products of manufacture. The arithmetic circuit may further include at least one of a floating-point-to-log-converter and/or a second of log-calculators. The arithmetic circuit may further include third and fourth log-arithmetic-units providing altered log domain numbers to third and fourth exponential calculators.
摘要翻译：一种接收号码并使用指令的方法和装置，用于产生接近数字的平方根，倒数或倒数平方根的数字。产生的数字作为该过程的产物。在图形加速器中使用结果编号。装置优选地包括对数计算器，对数运算单元和指数计算器。对数计算器和指数计算器中的至少一个包括实现非线性计算器。非线性计算器可以使用中频带滤波器，异常去除电路中的至少一个。本发明包括算术电路，对数计算器，对数运算单元和指数计算器。算术电路，对数计算器，对数运算单元和指数计算器作为制造产品。算术电路还可以包括浮点对数转换器和/或第二对数计算器中的至少一个。算术电路还可以包括向第三和第四指数计算器提供改变的对数域数的第三和第四对数运算单元。

2. 发明授权

US07284027B2 Method and apparatus for high speed calculation of non-linear functions and networks using non-linear function calculations for digital signal processing 失效
标题翻译：用于数字信号处理的非线性函数计算的非线性函数和网络的高速计算的方法和装置
公开(公告)号：US07284027B2
公开(公告)日：2007-10-16
申请号：US10226735
申请日：2002-08-22
申请人： Earle Willis Jennings, III , George Landers
发明人： Earle Willis Jennings, III , George Landers
IPC分类号： G06F7/52
CPC分类号： G06F1/0307 , G06F7/4806 , G06F7/5235 , G06F7/57 , G06F17/5045
摘要： The invention includes apparatus and methods for high-speed calculation of non-linear functions based upon a shifted adder and a offset generator. Various implementations may preferably include a input preprocessor and/or an output post processor. The invention includes a family of core cells built from instances of these calculators providing an upward, functionally compatible, extension to a family of Application Specific Integrated Circuit (ASIC) core cells. All of these core cells consistently provide the ability to perform high speed DSP tasks including Fast Fourier Transforms (FFTs), Finite Impulse Response (FIR) filters and Infinite Impulse Response (IIR) filters. The core cells built from the calculators can concurrently perform many non-linear function calculations. The core cells can switch between tasks every clock cycle.
摘要翻译：本发明包括用于基于移位的加法器和偏移发生器高速计算非线性函数的装置和方法。各种实现可以优选地包括输入预处理器和/或输出后处理器。本发明包括从这些计算器的实例构建的一系列核心单元，向专用集成电路（ASIC）核心单元系列提供向上的功能上兼容的扩展。所有这些核心单元一直提供执行高速DSP任务的能力，包括快速傅里叶变换（FFT），有限脉冲响应（FIR）滤波器和无限脉冲响应（IIR）滤波器。从计算器构建的核心单元可以同时执行许多非线性函数计算。核心单元可以在每个时钟周期之间切换任务。

3. 发明申请

US20060248137A1 APPARATUS AND METHOD FOR IMPLEMENTING FLOATING POINT ADDITIVE AND SHIFT OPERATIONS 失效
标题翻译：实施浮动点添加剂和移动操作的装置和方法
公开(公告)号：US20060248137A1
公开(公告)日：2006-11-02
申请号：US11380613
申请日：2006-04-27
申请人： George Landers , Earle Jennings
发明人： George Landers , Earle Jennings
IPC分类号： G06F7/52
CPC分类号： G06F7/485 , G06F5/012
摘要： A floating point (FP) shifter for use with FP adders providing a shifted FP operand as a power of the exponent base (usually two) multiplied by a FP operand. First arithmetic processor using at least one FP shifter with FP adder. FP adder for N FP operands creating FP result, where N is at least three. Second arithmetic processor including at least one FP adder for N operands. Descriptions of FP shifter and FP adder for implementing their operational methods. Implementations of FP shifter and FP adder.
摘要翻译：与FP加法器一起使用的浮点（FP）移位器，提供移位的FP操作数作为指数基数（通常为2）乘以FP操作数的幂。使用FP加法器的至少一个FP移位器的第一算术处理器。 FP加法器，用于产生FP结果的N个FP操作数，其中N至少为3。第二运算处理器包括用于N个操作数的至少一个FP加法器。 FP移位器和FP加法器的描述，用于实现其操作方法。 FP移位器和FP加法器的实现。

4. 发明授权

US06247036B1 Processor with reconfigurable arithmetic data path 失效
标题翻译：具有可重构算术数据路径的处理器
公开(公告)号：US06247036B1
公开(公告)日：2001-06-12
申请号：US08787496
申请日：1997-01-21
申请人： George Landers , Earle Jennings , Tim B. Smith , Glen Haas
发明人： George Landers , Earle Jennings , Tim B. Smith , Glen Haas
IPC分类号： G06F1500
CPC分类号： G06F15/7867 , G06F7/483 , G06F7/49 , G06F7/49936 , G06F7/5443 , G06F9/30003 , G06F9/30054 , G06F9/3885 , G06F9/3893 , G06F9/3897 , G06F2207/3884
摘要： A reconfigurable processor includes at least three (3) MacroSequencers (10)-(16) which are configured in an array. Each of the MacroSequencers is operable to receive on a separate one of four buses (18) an input from the other three MacroSequencers and from itself in a feedback manner. In addition, a control bus (20) is operable to provide control signals to all of the MacroSequencers for the purpose of controlling the instruction sequence associated therewith and also for inputting instructions thereto. Each of the MacroSequencers includes a plurality of executable units having inputs and outputs and each for providing an associated execution algorithm. The outputs of the execution units are input to an output selector which selects the outputs for outputs on at least one external output and on at least one feedback path. An input selector (66) is provided having an input for receiving at least one external output and at least the feedback path. These are selected between for input to select ones of the execution units. An instruction memory (48) contains an instruction word that is operable to control configurations of the datapath through the execution units for a given instruction cycle. This instruction word can be retrieved from the instruction memory (48), the stored instructions therein sequenced through to change the configuration of the datapath for subsequent instruction cycles.
摘要翻译：可重配置处理器包括至少三个（3）MacroSequencers（10） - （16），其被配置成阵列。每个MacroSequencers可操作以在四个总线（18）中的另外一个上接收来自其他三个MacroSequencer的输入，并以反馈方式从其自身接收。此外，控制总线（20）可操作以向所有的MacroSequencers提供控制信号，以便控制与其相关联的指令序列，并且还用于向其输入指令。每个MacroSequencers包括多个具有输入和输出的可执行单元，并且每个可执行单元用于提供相关联的执行算法。执行单元的输出被输入到输出选择器，该输出选择器选择至少一个外部输出和至少一个反馈路径上的输出的输出。提供输入选择器（66），其具有用于接收至少一个外部输出和至少反馈路径的输入。在输入之间选择这些选择执行单元。指令存储器（48）包含指令字，该指令字可用于通过用于给定指令周期的执行单元来控制数据通路的配置。可以从指令存储器（48）检索该指令字，其中存储的指令被顺序地改变以用于随后的指令周期的数据路径的配置。

5. 发明授权

US08892620B2 Computer for Amdahl-compliant algorithms like matrix inversion 有权
标题翻译：用于Amdahl兼容算法的计算机，如矩阵求逆
公开(公告)号：US08892620B2
公开(公告)日：2014-11-18
申请号：US13500103
申请日：2010-10-07
申请人： Earle Jennings , George Landers
发明人： Earle Jennings , George Landers
IPC分类号： G06F7/00 , G06F17/16
CPC分类号： G06F9/3001 , G06F17/16
摘要： A family of computers is disclosed and claimed that supports simultaneous processes from the single core up to multi-chip Program Execution Systems (PES). The instruction processing of the instructed resources is local, dispensing with the need for large VLIW memories. The cores through the PES have maximum performance for Amdahl-compliant algorithms like matrix inversion, because the multiplications do not stall and the other circuitry keeps up. Cores with log based multiplication generators improve this performance by a factor of two for sine and cosine calculations in single precision floating point and have even greater performance for loge and ex calculations. Apparatus specifying, simulating, and/or layouts of the computer (components) are disclosed. Apparatus the computer and/or its components are disclosed.
摘要翻译：公开和声称一系列计算机支持从单个核心到多芯片程序执行系统（PES）的同时处理。指示资源的指令处理是局部的，不需要大型VLIW存储器。通过PES的核心对于像矩阵反演这样的Amdahl兼容算法具有最大性能，因为乘法不会停顿，而另一个电路保持不变。使用基于对数的乘法生成器的核心将单个精度浮点的正弦和余弦计算的性能提高了两倍，并且对于loge和ex计算具有更高的性能。公开了计算机（组件）的指定，模拟和/或布局的装置。公开了计算机和/或其组件的装置。

6. 发明申请

US20120203814A1 COMPUTER FOR AMDAHL-COMPLIANT ALGORITHMS LIKE MATRIX INVERSION 审中-公开
标题翻译：用于AMDAHL合规算法的计算机类似矩阵变换
公开(公告)号：US20120203814A1
公开(公告)日：2012-08-09
申请号：US13500103
申请日：2010-10-07
申请人： Earle Jennings , George Landers
发明人： Earle Jennings , George Landers
IPC分类号： G06F7/523 , G06F7/556
CPC分类号： G06F9/3001 , G06F17/16
摘要： A family of computers is disclosed and claimed that supports simultaneous processes from the single core up to multi-chip Program Execution Systems (PES). The instruction processing of the instructed resources is local, dispensing with the need for large VLIW memories. The cores through the PES have maximum performance for Amdahl-compliant algorithms like matrix inversion, because the multiplications do not stall and the other circuitry keeps up. Cores with log based multiplication generators improve this performance by a factor of two for sine and cosine calculations in single precision floating point and have even greater performance for loge and ex calculations. Apparatus specifying, simulating, and/or layouts of the computer (components) are disclosed. Apparatus the computer and/or its components are disclosed.
摘要翻译：公开和声称一系列计算机支持从单个核心到多芯片程序执行系统（PES）的同时处理。指示资源的指令处理是局部的，不需要大型VLIW存储器。通过PES的核心对于像矩阵反演这样的Amdahl兼容算法具有最大性能，因为乘法不会停顿，而另一个电路保持不变。使用基于对数的乘法生成器的核心将单个精度浮点的正弦和余弦计算的性能提高了两倍，并且对于loge和ex计算具有更高的性能。公开了计算机（组件）的指定，模拟和/或布局的装置。公开了计算机和/或其组件的装置。

7. 发明授权

US08069200B2 Apparatus and method for implementing floating point additive and shift operations 失效
标题翻译：实现浮点添加剂和换档操作的装置和方法
公开(公告)号：US08069200B2
公开(公告)日：2011-11-29
申请号：US11380613
申请日：2006-04-27
申请人： George Landers , Earle Jennings
发明人： George Landers , Earle Jennings
IPC分类号： G06F7/38 , G06F7/42 , G06F7/44 , H04N7/12 , H04N11/02 , H04N11/04
CPC分类号： G06F7/485 , G06F5/012
摘要： A floating point (FP) shifter for use with FP adders providing a shifted FP operand as a power of the exponent base (usually two) multiplied by a FP operand. First arithmetic processor using at least one FP shifter with FP adder. FP adder for N FP operands creating FP result, where N is at least three. Second arithmetic processor including at least one FP adder for N operands. Descriptions of FP shifter and FP adder for implementing their operational methods. Implementations of FP shifter and FP adder.
摘要翻译：与FP加法器一起使用的浮点（FP）移位器，提供移位的FP操作数作为指数基数（通常为2）乘以FP操作数的幂。使用FP加法器的至少一个FP移位器的第一算术处理器。 FP加法器，用于产生FP结果的N个FP操作数，其中N至少为3。第二运算处理器包括用于N个操作数的至少一个FP加法器。 FP移位器和FP加法器的描述，用于实现其操作方法。 FP移位器和FP加法器的实现。

8. 发明授权

US07617268B2 Method and apparatus supporting non-additive calculations in graphics accelerators and digital signal processors 失效
标题翻译：在图形加速器和数字信号处理器中支持非加法计算的方法和装置
公开(公告)号：US07617268B2
公开(公告)日：2009-11-10
申请号：US11036538
申请日：2005-01-13
申请人： Earle Jennings , George Landers , Robert Spence
发明人： Earle Jennings , George Landers , Robert Spence
IPC分类号： G06F7/38 , G06F7/552
CPC分类号： G06F7/57 , G06F1/0307 , G06F7/4806 , G06F7/5235
摘要： A method and apparatus receiving number and using instruction to create resulting number approximating one of square root, reciprocal, or reciprocal square root of number. The resulting number as a product of that process. Using resulting number in a graphics accelerator. Apparatus preferably includes log-calculator, log-arithmetic-unit, and exponential-calculator. At least one of log-calculator and exponential-calculator include implementation non-linear calculator. The non-linear calculators may use at least one of mid-band-filter, outlier-removal-circuit. The invention includes making arithmetic circuit, log-calculator, log-arithmetic-unit and exponential-calculator. The arithmetic circuit, log-calculator, log-arithmetic-unit and exponential-calculator as products of manufacture. The arithmetic circuit may further include at least one of a floating-point-to-log-converter and/or a second of log-calculators. The arithmetic circuit may further include third and fourth log-arithmetic-units providing altered log domain numbers to third and fourth exponential calculators.
摘要翻译：接收数字和使用指令的方法和装置，以产生近似数字的平方根，倒数或倒数平方根之一的数字。产生的数字作为该过程的产物。在图形加速器中使用结果编号。装置优选地包括对数计算器，对数运算单元和指数计算器。对数计算器和指数计算器中的至少一个包括实现非线性计算器。非线性计算器可以使用中频带滤波器，异常去除电路中的至少一个。本发明包括算术电路，对数计算器，对数运算单元和指数计算器。算术电路，对数计算器，对数运算单元和指数计算器作为制造产品。算术电路还可以包括浮点对数转换器和/或第二对数计算器中的至少一个。算术电路还可以包括向第三和第四指数计算器提供改变的对数域数的第三和第四对数运算单元。

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