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1. 发明申请

US20180189031A1 MULTIPLICATION OPERATIONS IN MEMORY 审中-公开
公开(公告)号：US20180189031A1
公开(公告)日：2018-07-05
申请号：US15905083
申请日：2018-02-26
申请人： Micron Technology, Inc.
发明人： Sanjay Tiwari
IPC分类号： G06F7/523 , G11C7/10
CPC分类号： G06F7/523 , G06F7/53 , G06G7/16 , G11C7/1006 , G11C11/4091 , H03K19/17732
摘要： Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

2. 发明申请

US20170323677A1 MEMCAPACITIVE CROSS-BAR ARRAY FOR DETERMINING A DOT PRODUCT 审中-公开
公开(公告)号：US20170323677A1
公开(公告)日：2017-11-09
申请号：US15522344
申请日：2014-10-28
申请人： Hewlett Packard Enterprise Development LP
发明人： Ning Ge , John Paul Strachan , Jianhua Yang , Miao Hu
IPC分类号： G11C11/24 , G06G7/16 , G11C11/34
CPC分类号： G11C11/24 , G06G7/16 , G11C11/34
摘要： A method of obtaining a dot product includes applying a programming signal to a number of capacitive memory devices coupled at a number of junctions formed between a number of row lines and a number of column lines. The programming signal defines a number of values within a matrix. The method further includes applying a vector signal. The vector signal defines a number of vector values to be applied to the capacitive memory devices.

3. 发明授权

US09748935B2 Signal calculator 有权
公开(公告)号：US09748935B2
公开(公告)日：2017-08-29
申请号：US15166847
申请日：2016-05-27
申请人： FAIRCHILD KOREA SEMICONDUCTOR LTD.
发明人： Taesung Kim , Seunguk Yang , Youngbae Park
IPC分类号： H03K4/06 , H03K5/00 , G06G7/16 , H03K4/502 , H03K4/94
CPC分类号： H03K5/00 , G06G7/16 , H03K4/502 , H03K4/94
摘要： Examples of a signal calculator include a voltage multiplier and a time divider. The voltage multiplier copies time information corresponding to a first voltage and generates a third voltage using a second current corresponding to a second voltage during a first period corresponding to the copied time information. The time divider generates an output according to a result of comparing a voltage generated by a first current on the basis of a voltage corresponding to a first time with a second voltage corresponding to a second time.

4. 发明申请

US20170178725A1 MEMRISTIVE DOT PRODUCT ENGINE FOR VECTOR PROCESSING 审中-公开
公开(公告)号：US20170178725A1
公开(公告)日：2017-06-22
申请号：US15325543
申请日：2014-10-29
申请人： Hewlett Packard Enterprise Development LP
发明人： Jianhua Yang , Miao Hu , John Paul Strachan , Ning Ge
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G06F3/03 , G06G7/16 , G11C13/0021 , G11C13/003 , G11C13/0064 , G11C2213/79
摘要： A memristive dot-product system for vector processing is described. The memristive dot-product system includes a crossbar array having a number of memory elements. Each memory element includes a memristor. Each memory element includes a transistor. The system also includes a vector input register. The system also includes a vector output register.

5. 发明授权

US09553568B2 Frequency multiplier 有权
标题翻译：倍频器
公开(公告)号：US09553568B2
公开(公告)日：2017-01-24
申请号：US14925344
申请日：2015-10-28
申请人： Mitsubishi Electric Corporation
发明人： Hitoshi Kurusu , Yoshihiro Tsukahara
IPC分类号： G06G7/16 , H03B19/10 , H03B19/14 , H03K5/00
CPC分类号： H03K5/00006 , G06G7/16 , H03B19/10 , H03B19/14
摘要： A frequency multiplier includes an input terminal, an output terminal, a first transistor having a first gate to which a radiofrequency signal is input from the input terminal, a first drain from which an output signal is issued to the output terminal, and a first source, a second transistor having a second gate, a second source to which the radiofrequency signal is input from the input terminal, and a second drain from which an output signal is issued to the output terminal, and a stabilizing resistor which is a resistor connected to the second gate, wherein no resistor exists on the path for the radiofrequency signal, and wherein the stabilizing resistor suppresses a reflex gain produced by the second transistor.
摘要翻译：倍频器包括输入端子，输出端子，具有从输入端子输入射频信号的第一栅极的第一晶体管，向输出端子发出输出信号的第一漏极，以及第一源极，具有第二栅极的第二晶体管，从输入端子输入射频信号的第二源极和向输出端子发出输出信号的第二漏极，以及稳定电阻器，其是连接到所述第二栅极，其中在所述射频信号的路径上不存在电阻器，并且其中所述稳定电阻器抑制由所述第二晶体管产生的反射增益。

6. 发明申请

US20160117527A1 COMPACT CMOS CURRENT-MODE ANALOG MULTIFUNCTION CIRCUIT 有权
标题翻译：紧凑型CMOS电流模式模拟多功能电路
公开(公告)号：US20160117527A1
公开(公告)日：2016-04-28
申请号：US14526474
申请日：2014-10-28
申请人： KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
发明人： EYAS SALEH AL-SUHAIBANI , MUNIR A. AL-ABSI
IPC分类号： G06G7/16
CPC分类号： G06G7/16
摘要： The compact CMOS current-mode analog multifunction circuit is based on an implementation using MOSFETs operating in a sub-threshold region and forming two overlapping translinear loops capable of performing multiplication, division, controllable gain current amplifier, current mode differential amplifier, and differential-input single-output current amplifier.
摘要翻译：紧凑型CMOS电流模式模拟多功能电路基于使用在亚阈值区域中操作的MOSFET的实现，并形成能够执行乘法，分频，可控增益电流放大器，电流模式差分放大器和差分输入的两个重叠的跨线性回路单输出电流放大器。

7. 发明申请

US20130176067A1 COMPACT HIGH LINEARITY MMIC BASED FET RESISTIVE MIXER 有权
标题翻译：紧凑的高线性MMIC基FET电阻式混频器
公开(公告)号：US20130176067A1
公开(公告)日：2013-07-11
申请号：US13783589
申请日：2013-03-04
申请人： ViaSat, Inc.
发明人： Kenneth V. Buer
IPC分类号： G06G7/16
CPC分类号： G06G7/16 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D2200/0088
摘要： A MMIC (microwave monolithic integrated circuit) based FET mixer and method for the same is provided. In particular, adjacent transistors, such as FETs (field effect transistors) share terminals reducing physical layout separation and interconnections. A smaller die size is realized with the improved system geometry herein provided.
摘要翻译：提供了一种基于MMIC（微波单片集成电路）的FET混频器及其方法。特别地，诸如FET（场效应晶体管）的相邻晶体管共享终端，从而减少物理布局分离和互连。使用本文提供的改进的系统几何形状实现较小的模具尺寸。

8. 发明申请

US20120154015A1 ANALOG MULTIPLIER 失效
标题翻译：模拟乘法器
公开(公告)号：US20120154015A1
公开(公告)日：2012-06-21
申请号：US13047211
申请日：2011-03-14
申请人： Praveen Varma Nadimpalli , Joseph Hubert Colles
发明人： Praveen Varma Nadimpalli , Joseph Hubert Colles
IPC分类号： G06G7/16
CPC分类号： G06G7/16
摘要： An exemplary embodiment of an analog multiplier may include a voltage controlled resistance circuit, a first transistor and a second transistor, where the resistance of the voltage controlled resistance circuit is based upon a first input voltage. The current passing through the voltage controlled resistance circuit is based upon a second input voltage. The first transistor and the second transistor form a current mirror to mirror the current passing through the voltage controlled resistance circuit to provide a power supply control current to a wideband code division multiple access radio frequency power amplifier.
摘要翻译：模拟乘法器的示例性实施例可以包括电压控制电阻电路，第一晶体管和第二晶体管，其中电压控制电阻电路的电阻基于第一输入电压。通过压控电阻电路的电流基于第二输入电压。第一晶体管和第二晶体管形成电流镜以反射通过压控电阻电路的电流，以向宽带码分多址射频功率放大器提供电源控制电流。

9. 发明申请

US20110285451A1 PRECISION VOLTAGE DIVIDER 审中-公开
标题翻译：精密电压分压器
公开(公告)号：US20110285451A1
公开(公告)日：2011-11-24
申请号：US12784303
申请日：2010-05-20
申请人： Robert Alan Neidorff
发明人： Robert Alan Neidorff
IPC分类号： G06G7/16
CPC分类号： G06G7/16
摘要： A circuit for producing a quotient of two input voltages, Vy and Vx has a resistor across which said two input voltages are selectively successively applied. An operational amplifier has a reference potential (Vref) applied to one input, and a tap selectively connectable at one side to various points of the resistor is connected at its other side to the other input of the operational amplifier. The tap also provides a voltage output node of the circuit. After the tap has been configured with input voltage Vy applied across the resistor so that a voltage on the output node is substantially equal to the reference potential (Vref), when the input voltage Vx is applied across the resistor, a voltage on the output node represents a quotient of the input voltages Vy and Vx.
摘要翻译：用于产生两个输入电压的商的电路Vy和Vx具有电阻器，所述两个输入电压被选择性地连续地施加。运算放大器具有施加到一个输入端的参考电位（Vref），并且在一侧的选择性地可连接到电阻器的各个点的抽头在另一侧连接到运算放大器的另一个输入端。抽头还提供电路的电压输出节点。在分接头配置有施加在电阻器两端的输入电压Vy之后，使得输出节点上的电压基本上等于参考电位（Vref），当输入电压Vx施加在电阻器两端时，输出节点上的电压表示输入电压Vy和Vx的商。

10. 发明授权

US08010591B2 Four-gate transistor analog multiplier circuit 有权
标题翻译：四门晶体管模拟乘法电路
公开(公告)号：US08010591B2
公开(公告)日：2011-08-30
申请号：US11804893
申请日：2007-05-21
申请人： Mohammad M. Mojarradi , Benjamin Blalock , Sorin Cristoloveanu , Suheng Chen , Kerem Akarvardar
发明人： Mohammad M. Mojarradi , Benjamin Blalock , Sorin Cristoloveanu , Suheng Chen , Kerem Akarvardar
IPC分类号： G06E3/00
CPC分类号： G06G7/16
摘要： A differential output analog multiplier circuit utilizing four G4-FETs, each source connected to a current source. The four G4-FETs may be grouped into two pairs of two G4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.
摘要翻译：使用四个G4-FET的差分输出模拟乘法器电路，每个源极连接到电流源。四个G4-FET可以分成两对，每对两个G4-FET，其中一对具有连接到负载的漏极，另一对的漏极连接到另一个负载。差分输出电压在两个负载下进行。在一个实施例中，对于每个G4-FET，第一和第二结门各自连接在一起，其中第一输入电压施加到每对的前门，并且第二输入电压施加到每个的第一结门对。描述和要求保护其他实施例。

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