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1. 发明申请

US20120057106A1 POLARIZER AND LIQUID CRYSTAL DISPLAY 审中-公开
标题翻译：极化和液晶显示
公开(公告)号：US20120057106A1
公开(公告)日：2012-03-08
申请号：US13227440
申请日：2011-09-07
申请人： Kun Sik PARK , Kyu Ha Baek , Lee Mi Do
发明人： Kun Sik PARK , Kyu Ha Baek , Lee Mi Do
IPC分类号： G02F1/1335
CPC分类号： G02F1/133528 , G02F1/134336 , G02F2001/133548 , G02F2001/133565 , G02F2001/134318
摘要： Provided are a polarizer and a liquid crystal display (LCD) in which wire grid polarizers are formed on a thin film transistor substrate and a color filter substrate, respectively, so that it is possible to reduce fabrication cost and the number of processes and decrease the thickness of the LCD. An LCD includes a thin film transistor substrate, a color filter substrate opposite to the thin film transistor substrate, and a liquid crystal layer positioned between the thin film transistor substrate and the color filter substrate. In the LCD, wire grid polarizing patterns are formed on the thin film transistor substrate and the color filter substrate, respectively.
摘要翻译：提供一种偏振器和液晶显示器（LCD），其中分别在薄膜晶体管基板和滤色器基板上形成线栅偏振器，使得可以降低制造成本和工艺数量，并减少 LCD的厚度。 LCD包括薄膜晶体管基板，与薄膜晶体管基板相对的滤色器基板，以及位于薄膜晶体管基板和滤色器基板之间的液晶层。在LCD中，线栅偏振图案分别形成在薄膜晶体管基板和滤色器基板上。

2. 发明申请

US20110097853A1 VIA FORMING METHOD AND METHOD OF MANUFACTURING MULTI-CHIP PACKAGE USING THE SAME 有权
标题翻译：通过形成方法和使用其制造多芯片包的方法
公开(公告)号：US20110097853A1
公开(公告)日：2011-04-28
申请号：US12835289
申请日：2010-07-13
申请人： Dong Pyo KIM , Kyu Ha Baek , Kun Sik Park , Lee Mi Do
发明人： Dong Pyo KIM , Kyu Ha Baek , Kun Sik Park , Lee Mi Do
IPC分类号： H01L21/768 , H01L21/50
CPC分类号： H01L21/76898 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/05599 , H01L2224/13025 , H01L2224/16147 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/15311 , H01L2924/15788 , H01L2224/05552 , H01L2924/00
摘要： A via forming method is provided. The via forming method includes: forming via-holes in a substrate; putting the substrate having the via-holes in a first solution to fill the via-holes with the first solution; sinking the metal particles into the via-holes by supplying a second solution containing metal particles to the first solution, in which there is the substrate; and performing a first curing process of heat-treating the substrate having the via-holes filled with the metal particles so as to form vias in the via-holes. Further, a method of manufacturing a multi-chip package using the via forming method is provided.
摘要翻译：提供通孔形成方法。通孔形成方法包括：在基板中形成通孔; 将具有通孔的基板放置在第一溶液中以用第一溶液填充通孔; 通过向其中存在基底的第一溶液提供含有金属颗粒的第二溶液将金属颗粒沉入通孔中; 并进行热处理具有填充有金属颗粒的通孔的基板的第一固化工艺，以便在通孔中形成通路。此外，提供了使用通孔形成方法制造多芯片封装的方法。

3. 发明申请

US20090146238A1 CMOS-BASED PLANAR TYPE SILICON AVALANCHE PHOTO DIODE USING SILICON EPITAXIAL LAYER AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：使用硅外延层的基于CMOS的平面型硅氧化物照相二极管及其制造方法
公开(公告)号：US20090146238A1
公开(公告)日：2009-06-11
申请号：US12195166
申请日：2008-08-20
申请人： Yong Sun Yoon , Kun Sik Park , Jong Moon Park , Bo Woo Kim , Jin Yeong Kang
发明人： Yong Sun Yoon , Kun Sik Park , Jong Moon Park , Bo Woo Kim , Jin Yeong Kang
IPC分类号： H01L31/103 , H01L31/18
CPC分类号： H01L31/107
摘要： A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes are formed.
摘要翻译：使用硅外延层的基于互补金属氧化物半导体（CMOS）的平面型雪崩光电二极管（APD）和制造该APD的方法，所述光电二极管包括：衬底; 在衬底中形成的第一导电类型的阱层; 通过低能离子注入形成在第一导电类型的阱层中的雪崩嵌入结; 形成在雪崩嵌入结的硅外延层; 由所述第一导电类型的阱层的表面的一部分形成在所述雪崩嵌入结中并形成p-n结的与所述第一导电类型相反的第二导电类型的掺杂区域; 分别形成在第二导电类型的掺杂区域上的正极和负极以及从第二导电类型的掺杂区域分离的第一导电类型的阱层; 以及形成在除了形成正极和负极的窗口之外的整个表面上的氧化物层。

4. 发明授权

US08981937B2 RFID tag 有权
标题翻译： RFID标签
公开(公告)号：US08981937B2
公开(公告)日：2015-03-17
申请号：US13294359
申请日：2011-11-11
申请人： Ji Man Park , Lee Mi Do , Kyu Ha Baek , Kun Sik Park , Dong Pyo Kim , Jong Chang Woo , Zin Sig Kim , Joo Yeon Kim , Ye Sul Jeong , Yong Hyun Ham
发明人： Ji Man Park , Lee Mi Do , Kyu Ha Baek , Kun Sik Park , Dong Pyo Kim , Jong Chang Woo , Zin Sig Kim , Joo Yeon Kim , Ye Sul Jeong , Yong Hyun Ham
IPC分类号： G08B13/14 , G06K19/073
CPC分类号： G06K19/07345
摘要： An RFID tag includes: an antenna receiving an RF signal from a reader; an AFE (analog front end) generating voltage using the RF signal; and one or more switches interposed between the antenna and the AFE and controlling the connection between the antenna and the AFE through the switch operation.
摘要翻译： RFID标签包括：从读取器接收RF信号的天线; 使用RF信号产生电压的AFE（模拟前端）; 以及插入在天线和AFE之间的一个或多个开关，并且通过开关操作来控制天线和AFE之间的连接。

5. 发明申请

US20120161941A1 RFID TAG 有权
标题翻译： RFID标签
公开(公告)号：US20120161941A1
公开(公告)日：2012-06-28
申请号：US13294359
申请日：2011-11-11
申请人： Ji Man PARK , Lee Mi DO , Kyu Ha BAEK , Kun Sik PARK , Dong Pyo KIM , Jong Chang WOO , Zin Sig KIM , Joo Yeon KIM , Ye Sul JEONG , Yong Hyun HAM
发明人： Ji Man PARK , Lee Mi DO , Kyu Ha BAEK , Kun Sik PARK , Dong Pyo KIM , Jong Chang WOO , Zin Sig KIM , Joo Yeon KIM , Ye Sul JEONG , Yong Hyun HAM
IPC分类号： G06K7/01
CPC分类号： G06K19/07345
摘要： An RFID tag includes: an antenna receiving an RF signal from a reader; an AFE (analog front end) generating voltage using the RF signal; and one or more switches interposed between the antenna and the AFE and controlling the connection between the antenna and the AFE through the switch operation.
摘要翻译： RFID标签包括：从读取器接收RF信号的天线; 使用RF信号产生电压的AFE（模拟前端）; 以及插入在天线和AFE之间的一个或多个开关，并且通过开关操作来控制天线和AFE之间的连接。

6. 发明申请

US20110147787A1 ORGANIC LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：有机发光二极管及其制造方法
公开(公告)号：US20110147787A1
公开(公告)日：2011-06-23
申请号：US12974708
申请日：2010-12-21
申请人： Lee Mi DO , Kun Sik Park , Ji Man Park , Dong Pyo Kim , Jin Yeong Kang , Kyu Ha Baek
发明人： Lee Mi DO , Kun Sik Park , Ji Man Park , Dong Pyo Kim , Jin Yeong Kang , Kyu Ha Baek
IPC分类号： H01L51/52 , H01L51/56
CPC分类号： H01L51/5212 , H01L51/5228
摘要： An organic light emitting diode (OLED) and a method for manufacturing the same are provided. In the OLED, patterned metal electrodes are positioned on one or more of upper and lower portions of a light emission layer to allow light generated from the light emission layer to emit to an area between the patterned metal electrodes.
摘要翻译：提供有机发光二极管（OLED）及其制造方法。在OLED中，图案化的金属电极位于发光层的上部和下部的一个或多个上，以允许从发光层产生的光发射到图案化的金属电极之间的区域。

7. 发明申请

US20110147468A1 RFID TAG 审中-公开
标题翻译： RFID标签
公开(公告)号：US20110147468A1
公开(公告)日：2011-06-23
申请号：US12970394
申请日：2010-12-16
申请人： Ji Man PARK , Lee Mi Do , Kyu Ha Baek , Kun Sik Park , Dong Pyo Kim
发明人： Ji Man PARK , Lee Mi Do , Kyu Ha Baek , Kun Sik Park , Dong Pyo Kim
IPC分类号： G06K19/073
CPC分类号： G06K19/0704 , G06K19/0723
摘要： Provided is a radio frequency identification (RFID) tag whose data can be stably read at a long distance on the basis of a passive RFID tag. The RFID tag includes a rechargeable unit charged to a predetermined voltage, and a power source including a direct current (DC) power source including a rectifier for converting an RF signal into DC power and a regulator for supplying a predetermined DC voltage, an interceptor disposed between the rechargeable unit and the DC power source to connecting or disconnecting the power to the rechargeable unit, and an overvoltage preventor connected to an output terminal of the DC power source in parallel.
摘要翻译：提供了一种射频识别（RFID）标签，其数据可以在无源RFID标签的基础上以长距离稳定地读取。 RFID标签包括充电到预定电压的可充电单元和包括直流（DC）电源的电源，该直流电源包括用于将RF信号转换成直流电力的整流器和用于提供预定DC电压的调节器，设置的拦截器在可再充电单元和直流电源之间，连接或断开与可再充电单元的电力，以及并联连接到DC电源的输出端子的过电压防止器。

8. 发明授权

US07141464B2 Method of fabricating T-type gate 失效
标题翻译：制造T型门的方法
公开(公告)号：US07141464B2
公开(公告)日：2006-11-28
申请号：US11179983
申请日：2005-07-12
申请人： Jong Moon Park , Kun Sik Park , Seong Wook Yoo , Yong Sun Yoon , Sang Gi Kim , Yoon Kyu Bae , Byung Won Lim , Jin Gun Koo , Bo Woo Kim
发明人： Jong Moon Park , Kun Sik Park , Seong Wook Yoo , Yong Sun Yoon , Sang Gi Kim , Yoon Kyu Bae , Byung Won Lim , Jin Gun Koo , Bo Woo Kim
IPC分类号： H01L21/338
CPC分类号： H01L21/28587
摘要： Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible to readily perform a compound semiconductor device manufacturing process, and to reduce manufacturing cost by means of the increase of manufacturing yield and the simplification of manufacturing processes.
摘要翻译：提供一种制造T型栅极的方法，包括以下步骤：分别在衬底上形成预定厚度的第一光致抗蚀剂层，阻挡层和第二光致抗蚀剂层; 在所述第二光致抗蚀剂层和所述阻挡层上形成T型栅极的主体图案; 暴露第二光致抗蚀剂层的预定部分以形成T型栅极的头部图案，并且进行热处理工艺以在除了T型的头部图案之外的第二光致抗蚀剂层的预定区域处产生交联门; 在所得结构的整个表面上进行曝光处理，然后去除所述暴露部分; 在所得结构的整个表面上形成预定厚度的金属层，然后去除第一光致抗蚀剂层，阻挡层，产生交联的第二光致抗蚀剂层的预定区域和金属层，由此可以容易地进行化合物半导体器件制造工艺，并且通过增加制造成品率和简化制造工艺来降低制造成本。

9. 发明授权

US06284551B1 Capacitor and method for fabricating the same 有权
标题翻译：电容器及其制造方法
公开(公告)号：US06284551B1
公开(公告)日：2001-09-04
申请号：US09455791
申请日：1999-12-07
申请人： Won Cheol Cho , Kun Sik Park
发明人： Won Cheol Cho , Kun Sik Park
IPC分类号： H01L218242
CPC分类号： H01L21/76844 , H01L21/76802 , H01L21/76831 , H01L21/7687 , H01L27/10855 , H01L28/60
摘要： Capacitor and method for fabricating the same, which can simplify a fabrication process and reduce parasitic capacitances between signal lines, the capacitor including a first insulating layer formed on a substrate, a bitline patterned on the first insulating layer, a second insulating layer formed on the bitline, a first electrode formed on the second insulating layer with slopes at both sides, a dielectric film formed on the first electrode, a node contact formed on one side of the first electrode and in contact with the substrate, and a second electrode formed on the dielectric film and connected with the node contact electrically, and the method including the steps of (1) forming a first insulating layer on a substrate, and patterning a bitline on the first insulating layer, (2) forming a second insulating layer on an entire surface inclusive of the bitline, (3) depositing a first conductive material on the second insulating layer, (4) etching the first conductive material to form a first electrode with a sloped etch surface, (5) depositing a dielectric film on the first electrode, (6) etching the second insulating layer and the first insulating layer in succession to form a contact hole exposing the substrate, (7) depositing and etching a second conductive in the contact hole, to form a node contact, and (8) depositing and etching a third conductive material on the node contact, to form a second electrode.
摘要翻译：电容器及其制造方法，其可以简化制造工艺并减少信号线之间的寄生电容，电容器包括形成在衬底上的第一绝缘层，图案化在第一绝缘层上的位线，形成在第一绝缘层上的第二绝缘层位线，形成在具有两侧斜面的第二绝缘层上的第一电极，形成在第一电极上的电介质膜，形成在第一电极的一侧并与衬底接触的节点接触件，以及形成在第一电极上的第二电极所述电介质膜与所述节点接触电连接，所述方法包括以下步骤：（1）在衬底上形成第一绝缘层，并对所述第一绝缘层上的位线进行构图，（2）在第一绝缘层上形成第二绝缘层包括位线的整个表面，（3）在第二绝缘层上沉积第一导电材料，（4）蚀刻第一导电材料以形成具有倾斜蚀刻表面的第一电极，（5）在所述第一电极上沉积电介质膜，（6）连续蚀刻所述第二绝缘层和所述第一绝缘层以形成暴露所述衬底的接触孔，（7）蚀刻接触孔中的第二导体，形成节点接触，以及（8）沉积和蚀刻节点接触上的第三导电材料，以形成第二电极。

10. 发明授权

US07994553B2 CMOS-based planar type silicon avalanche photo diode using silicon epitaxial layer and method of manufacturing the same 有权
标题翻译：使用硅外延层的CMOS基平面型硅雪崩光电二极管及其制造方法
公开(公告)号：US07994553B2
公开(公告)日：2011-08-09
申请号：US12195166
申请日：2008-08-20
申请人： Yong Sun Yoon , Kun Sik Park , Jong Moon Park , Bo Woo Kim , Jin Yeong Kang
发明人： Yong Sun Yoon , Kun Sik Park , Jong Moon Park , Bo Woo Kim , Jin Yeong Kang
IPC分类号： H01L31/062
CPC分类号： H01L31/107
摘要： A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes are formed.
摘要翻译：使用硅外延层的基于互补金属氧化物半导体（CMOS）的平面型雪崩光电二极管（APD）和制造该APD的方法，所述光电二极管包括：衬底; 在衬底中形成的第一导电类型的阱层; 通过低能离子注入形成在第一导电类型的阱层中的雪崩嵌入结; 形成在雪崩嵌入结的硅外延层; 由所述第一导电类型的阱层的表面的一部分形成在所述雪崩嵌入结中并形成p-n结的与所述第一导电类型相反的第二导电类型的掺杂区域; 分别形成在第二导电类型的掺杂区域上的正极和负极以及从第二导电类型的掺杂区域分离的第一导电类型的阱层; 以及形成在除了形成正极和负极的窗口之外的整个表面上的氧化物层。

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