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1. 发明授权

US08667049B2 Massively parallel supercomputer 有权
标题翻译：大容量并行超级计算机
公开(公告)号：US08667049B2
公开(公告)日：2014-03-04
申请号：US13566024
申请日：2012-08-03
申请人： Matthias A. Blumrich , Dong Chen , George L. Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampap , Philip Heidlberger , Gerard V. Kopcsay , Lawrence S. Mok , Todd E. Takken
发明人： Matthias A. Blumrich , Dong Chen , George L. Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampap , Philip Heidlberger , Gerard V. Kopcsay , Lawrence S. Mok , Todd E. Takken
IPC分类号： G06F15/173
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.
摘要翻译：数百个teraOPS级别的新型大规模并行超级计算机包括基于片上系统技术的节点架构，即每个处理节点包括单个专用集成电路（ASIC）。在每个ASIC节点内是多个处理元件，每个处理元件由中央处理单元（CPU）和多个浮点处理器组成，以实现计算性能，封装密度，低成本以及功率和冷却要求的最佳平衡。单个节点内的多个处理器单独或同时工作在要解决的特定算法所要求的计算或通信的任何组合上。片上系统ASIC节点通过多个独立网络互连，从而最大限度地最大限度地提高了分组通信吞吐量并最大限度地减少了延迟。多个网络包括用于并行算法消息传递的三个高速网络，包括Torus，全局树和提供全局障碍和通知功能的全球异步网络。

2. 发明授权

US07947599B2 Laser annealing for 3-D chip integration 有权
标题翻译：激光退火3-D芯片集成
公开(公告)号：US07947599B2
公开(公告)日：2011-05-24
申请号：US12018756
申请日：2008-01-23
申请人： Howard H. Chen , Louis C. Hsu , Lawrence S. Mok , J. Campbell Scott
发明人： Howard H. Chen , Louis C. Hsu , Lawrence S. Mok , J. Campbell Scott
IPC分类号： H01L21/44
CPC分类号： H01L21/324 , H01L21/268 , H01L24/01 , H01L25/0657 , H01L27/0688 , H01L2225/06513 , H01L2225/06541 , H01L2924/14 , H01L2924/00
摘要： A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.
摘要翻译：公开了一种用于退火具有至少两个堆叠层的层叠半导体结构的激光退火方法。激光束聚焦在堆叠层的下层。然后扫描激光束以退火下层中的特征。然后将激光束聚焦在堆叠层的上层上，并且激光束被扫描以退火上层中的特征。激光器的波长小于1微米。激光束的光束尺寸，焦深，能量投射和扫描速度是可编程的。较低层中的特征偏离上层中的特征，使得这些特征不沿着与激光束的路径平行的平面重叠。堆叠层中的每一个包括诸如晶体管的有源器件。此外，第一层和第二层可以同时退火。

3. 发明申请

US20100117209A1 MULTIPLE CHIPS ON A SEMICONDUCTOR CHIP WITH COOLING MEANS 审中-公开
标题翻译：具有冷却方式的半导体芯片上的多个芯片
公开(公告)号：US20100117209A1
公开(公告)日：2010-05-13
申请号：US11680311
申请日：2007-02-28
申请人： Raschid J. Bezama , Minhua Lu , Lawrence S. Mok
发明人： Raschid J. Bezama , Minhua Lu , Lawrence S. Mok
IPC分类号： H01L23/52 , H01L23/46
CPC分类号： H01L23/427 , F28D15/046 , H01L25/065 , H01L25/18 , H01L2224/05001 , H01L2224/05009 , H01L2224/05026 , H01L2224/05568 , H01L2224/0557 , H01L2224/05647 , H01L2224/16145 , H01L2224/16225 , H01L2225/06562 , H01L2225/06589 , H01L2924/00014 , H01L2924/15311 , H01L2224/05099
摘要： The present invention is directed to a method of packaging multiple semiconductor chips on a second semiconductor chips with a built-in efficient cooling means. One embodiment is to place two multiple chip stacks on opposing sides of a vapor chamber for transferring heat away from the semiconductor chips. Another embodiment is to construct a vapor chamber with a substrate such that at least one multiple chip stack is embedded inside the vapor chamber.
摘要翻译：本发明涉及一种利用内置高效冷却装置在多个半导体芯片上封装多个半导体芯片的方法。一个实施例是将两个多个芯片堆放置在蒸气室的相对侧上，以将热量从半导体芯片传送出去。另一个实施例是构造具有衬底的蒸汽室，使得至少一个多个芯片堆叠被嵌入在蒸气室内。

4. 发明申请

US20090008129A1 COOLING OF SUBSTRATE USING INTERPOSER CHANNELS 有权
标题翻译：使用插入式通道冷却基板
公开(公告)号：US20090008129A1
公开(公告)日：2009-01-08
申请号：US12212925
申请日：2008-09-18
申请人： Minhua Lu , Lawrence S. Mok
发明人： Minhua Lu , Lawrence S. Mok
IPC分类号： H05K1/00
CPC分类号： H01L23/427 , F28D15/0266 , H01L23/433 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/10253 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49165 , Y10T29/49204 , H01L2924/00 , H01L2224/0401
摘要： A structure. The structure includes a substrate and an interposer. The substrate includes a heat source and N continuous substrate channels on a first side of the substrate (N≧2). The interposer includes N continuous interposer channels coupled to the N substrate channels to form M continuous loops (1≦M≦N). Each loop independently consists of K substrate channels and K interposer channels in an alternating sequence. For each loop, K is at least 1 and is subject to an upper limit consistent with a constraint of the M loops collectively consisting of the N interposer channels and the N substrate channels. Each loop is independently open ended or closed. The first side of the substrate is connected to the interposer. The interposer is adapted to be thermally coupled to a heat sink such that the interposer is interposed between the substrate and the heat sink.
摘要翻译：一个结构。该结构包括基板和插入件。衬底在衬底的第一侧上包括热源和N个连续衬底通道（N> = 2）。插入器包括耦合到N个衬底沟道的N个连续插入器通道，以形成M个连续环（1≤M≤N）。每个回路以交替顺序独立地由K个衬底通道和K个插入器通道组成。对于每个循环，K至少为1，并且受到与由N个插入物通道和N个底物通道组成的M个回路的约束一致的上限。每个循环是独立开放的或封闭的。衬底的第一面连接到插入器。插入器适于热耦合到散热器，使得插入器插入在基板和散热器之间。

5. 发明申请

US20080166492A1 METAL-GRAPHITE FOAM COMPOSITE AND A COOLING APPARATUS FOR USING THE SAME 审中-公开
标题翻译：金属石墨泡沫复合材料和使用它的冷却装置
公开(公告)号：US20080166492A1
公开(公告)日：2008-07-10
申请号：US11621163
申请日：2007-01-09
申请人： Minhua Lu , Lawrence S. Mok , Krystyna W. Semkow
发明人： Minhua Lu , Lawrence S. Mok , Krystyna W. Semkow
IPC分类号： B05D1/18
CPC分类号： H01L23/473 , B22F2998/10 , B22F2999/00 , C04B41/009 , C04B41/52 , C04B41/90 , C04B2111/00844 , C22C2001/1021 , H01L23/3733 , H01L23/433 , H01L2224/16 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , C04B41/4564 , C04B41/4572 , C04B41/5127 , C04B41/4517 , C04B41/4523 , C04B35/522 , C04B38/00 , C22C1/1015 , C04B41/00 , C25D5/54 , H01L2224/0401
摘要： A method of producing a metal-graphite foam composite, and particularly, the utilization thereof in connection with a cooling apparatus. Also provided is a cooling apparatus, such as a liquid cooler or alternatively, a heat sink for electronic heat-generating components, which employ the metal-graphite foam composite.
摘要翻译：一种金属 - 石墨发泡体复合体的制造方法，特别是与冷却装置的利用。还提供了采用金属 - 石墨泡沫复合材料的冷却装置，例如液体冷却器或替代地，用于电子发热部件的散热器。

6. 发明申请

US20080053640A1 Compliant vapor chamber chip packaging 有权
标题翻译：符合蒸汽室芯片封装
公开(公告)号：US20080053640A1
公开(公告)日：2008-03-06
申请号：US11513786
申请日：2006-08-31
申请人： Lawrence S. Mok
发明人： Lawrence S. Mok
IPC分类号： F28D15/00
CPC分类号： F28D15/02 , H01L23/427 , H01L23/4332 , H01L2924/0002 , H01L2924/00
摘要： An arrangement for improving the cooling efficiency of semiconductor chips. One embodiment is to construct a vapor chamber with one compliant surface for improving the efficiency of transferring heat from a semiconductor chip to the vapor chamber, and another embodiment is to construct a vapor chamber with the chip substrate such that the chips are embedded inside the vapor chamber. One surface of the vapor chamber has a flexible structure to enable the surface of the vapor chamber to be compliant with the surface of a chip or a heat sink device.
摘要翻译：一种用于提高半导体芯片的冷却效率的装置。一个实施例是构造具有一个柔性表面的蒸汽室，以提高从半导体芯片向蒸气室传递热量的效率，另一个实施例是构建具有芯片基板的蒸气室，使得芯片嵌入蒸汽内部房间。蒸汽室的一个表面具有柔性结构，以使得蒸气室的表面能够与芯片或散热装置的表面相一致。

7. 发明授权

US07180179B2 Thermal interposer for thermal management of semiconductor devices 失效
标题翻译：用于半导体器件热管理的热插入器
公开(公告)号：US07180179B2
公开(公告)日：2007-02-20
申请号：US10872575
申请日：2004-06-18
申请人： Lawrence S. Mok , Evan G. Colgan , Minhua Lu , Da-Yuan Shih
发明人： Lawrence S. Mok , Evan G. Colgan , Minhua Lu , Da-Yuan Shih
IPC分类号： H01L23/34 , H01L23/495
CPC分类号： H01L23/427 , H01L2224/16 , H01L2224/16225 , H01L2224/73253 , H01L2924/01019 , H01L2924/01078 , H01L2924/01322 , H01L2924/09701 , H01L2924/10158 , H01L2924/15311
摘要： A thermal interposer is provided for attachment to a surface of a semiconductor device. In one embodiment, the thermal interposer includes an upper plate having a bottom surface with a plurality of grooves and made of a material having high thermal conductivity, and a lower plate having a top surface with a plurality of grooves and made of a material having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the material of a semiconductor device that is bonded to the bottom surface of the lower plate. The bottom surface of the upper plate is hermetically bonded to the top surface of the lower plate so that a vapor chamber is formed by the upper and lower plates, and walls of the grooves on the top surface of the lower plate extend to within less than 250 microns from walls of the grooves on the bottom surface of the upper plate comprise a plurality of second walls the first walls.
摘要翻译：提供了用于附接到半导体器件的表面的热插入件。在一个实施例中，热插入件包括具有多个凹槽并由具有高导热性的材料制成的底表面的上板，以及具有多个凹槽的顶表面的下板，并由具有热膨胀系数与结合到下板的底面的半导体器件的材料的热膨胀系数基本相同。上板的底面与下板的顶面密封，从而通过上板和下板形成蒸气室，下板顶表面上的槽的壁延伸到小于在上板的底表面上的槽的壁250微米包括多个第二壁和第一壁。

8. 发明授权

US06829711B1 Personal website for electronic commerce on a smart java card with multiple security check points 有权
标题翻译：智能java卡上的电子商务个人网站，具有多个安全检查点
公开(公告)号：US06829711B1
公开(公告)日：2004-12-07
申请号：US09237387
申请日：1999-01-26
申请人： Thomas Y. Kwok , Lawrence S. Mok
发明人： Thomas Y. Kwok , Lawrence S. Mok
IPC分类号： H04K100
CPC分类号： G07F7/1008 , G06F21/32 , G06F21/33 , G06F21/34 , G06F21/445 , G06Q20/341 , G06Q20/363 , G06Q20/40145 , G07F7/0866
摘要： A Method and system are disclosed for accessing personal Web site or executing electronic commerce with security in a smart Java card. A personal Web site which includes personal or private information is stored in a personal smart Java card. Before a user can access the Web site stored in the smart Java card, the user is validated by any one of or in combination of PIN, facial images, hand images, eye image, voice characteristics, and finger prints. In addition, an encryption engine embedded in the smart Java card decodes and compares the entered PIN combined with a secure key or security certificate to verify the identity of the user. Before the bank account can be accessed freely by the user, the bank's computer system checks the combined secure data to ensure the authenticity of the card and the user's identity with multiple check points using Internet security protocols via Web browsers.
摘要翻译：公开了一种用于访问个人网站或在智能Java卡中执行具有安全性的电子商务的方法和系统。包含个人或私人信息的个人网站存储在个人智能Java卡中。在用户可以访问存储在智能Java卡中的网站之前，用户通过PIN，面部图像，手图像，眼睛图像，语音特征和指纹中的任何一个或其组合来验证用户。此外，嵌入在智能Java卡中的加密引擎解码并比较输入的PIN与安全密钥或安全证书的组合，以验证用户的身份。银行帐户可以由用户自由访问之前，银行的计算机系统将通过Web浏览器使用Internet安全协议检查组合的安全数据，以确保卡的真实性和多个检查点的用户身份。

9. 发明授权

US06306686B1 Method of fabricating an electronic package with interconnected chips 失效
标题翻译：制造具有互连芯片的电子封装的方法
公开(公告)号：US06306686B1
公开(公告)日：2001-10-23
申请号：US09487747
申请日：2000-01-19
申请人： Raymond Robert Horton , Alphonso Philip Lanzetta , Joseph Maryan Milewski , Lawrence S. Mok , Robert Kevin Montoye , Hussain Shaukatulla
发明人： Raymond Robert Horton , Alphonso Philip Lanzetta , Joseph Maryan Milewski , Lawrence S. Mok , Robert Kevin Montoye , Hussain Shaukatulla
IPC分类号： H01L2150
CPC分类号： H01L23/49822 , H01L23/49811 , H01L23/49833 , H01L24/45 , H01L24/48 , H01L2224/05599 , H01L2224/16145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/854 , H01L2224/85439 , H01L2224/85444 , H01L2224/8547 , H01L2924/00014 , H01L2924/01039 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： An electronic package which includes a circuitized substrate with a cavity and a first semiconductor chip positioned therein. The first chip is electrically coupled to conductive members located on the circuitized substrate. A second semiconductor chip is positioned on and electrically coupled to the first chip.
摘要翻译：一种电子封装，其包括具有空腔的电路化基板和位于其中的第一半导体芯片。第一芯片电耦合到位于电路化基板上的导电构件。第二半导体芯片位于第一芯片上并电耦合到第一芯片。

10. 发明授权

US5764314A Mechanical packaging and thermal management of flat mirror arrays 失效
公开(公告)号：US5764314A
公开(公告)日：1998-06-09
申请号：US754927
申请日：1996-11-25
申请人： Chandrasekhar Narayan , Evan Colgan , Kei-Hsiung Yang , Robert L. Melcher , Lawrence S. Mok , Leathen Shi , Thomas M. Cipolla
发明人： Chandrasekhar Narayan , Evan Colgan , Kei-Hsiung Yang , Robert L. Melcher , Lawrence S. Mok , Leathen Shi , Thomas M. Cipolla
IPC分类号： G02F1/13 , G02F1/133 , G02F1/1333 , G02F1/136 , G09F9/00 , H04N5/74
CPC分类号： G02F1/133385 , G02F1/133308 , G02F1/136 , G02F2001/133322 , G02F2001/133325
摘要： A liquid crystal element, a packaging structure providing thermal and alignment control, a display device including the same, and methods of fabrication and assembly are provided. The liquid crystal element includes: a semiconductor wafer, having microcircuitry and an array of reflective pixels; a layer of electro-optical responsive liquid crystal medium, of uniform thickness, disposed on the reflective pixels; a transparent conductive layer positioned on the liquid crystal, being substantially parallel to the reflective layers, to ensure a uniform thickness of the liquid crystal; and an insulative transparent layer provided on the conductive layer. The liquid crystal element is laminated to an optically flat substrate to limit the out-of-plane distortions thereof. The structure formed by element and substrate are disposed in a substrate holder which is mounted to a wiring board, and coupled to voltage sources for actuating the liquid crystal. During mounting, an aligning fixture is used to ensure proper orientation of the element relative to the related optical elements. Once the element is positioned, a heat sink is coupled to the rear surface of the substrate holder to dissipate heat.

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