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1. 发明授权

US08658999B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08658999B2
公开(公告)日：2014-02-25
申请号：US13728552
申请日：2012-12-27
申请人： Yoshifumi Nishi , Takao Marukame , Takayuki Ishikawa , Masato Koyama
发明人： Yoshifumi Nishi , Takao Marukame , Takayuki Ishikawa , Masato Koyama
IPC分类号： H01L29/02
CPC分类号： H01L45/14 , H01L27/2472 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/16
摘要： According to an embodiment, a semiconductor device includes first and second memristors. The first memristor includes a first electrode made of a first material, a second electrode made of a second material, and a first resistive switching film arranged between the first and second electrodes. The first resistive switching film is connected to both the first and second electrodes. The second memristor includes a third electrode made of a third material, a fourth electrode made of the second material, and a second resistive switching film arranged between the third and fourth electrodes. The second resistive switching film is connected to both the third and fourth electrodes. The work function of the first material is smaller than that of the second material. The work function of the third material is larger than that of the second material.
摘要翻译：根据实施例，半导体器件包括第一和第二忆阻器。第一忆阻器包括由第一材料制成的第一电极，由第二材料制成的第二电极和布置在第一和第二电极之间的第一电阻切换膜。第一电阻开关膜连接到第一和第二电极。第二忆阻器包括由第三材料制成的第三电极，由第二材料制成的第四电极和布置在第三和第四电极之间的第二电阻切换膜。第二电阻开关膜连接到第三和第四电极。第一材料的功函数小于第二材料的功函数。第三种材料的功函数大于第二种材料的功函数。

2. 发明申请

US20130234088A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20130234088A1
公开(公告)日：2013-09-12
申请号：US13728552
申请日：2012-12-27
申请人： Yoshifumi Nishi , Takao Marukame , Takayuki Ishikawa , Masato Koyama
发明人： Yoshifumi Nishi , Takao Marukame , Takayuki Ishikawa , Masato Koyama
IPC分类号： H01L45/00
CPC分类号： H01L45/14 , H01L27/2472 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/16
摘要： According to an embodiment, a semiconductor device includes first and second memristors. The first memristor includes a first electrode made of a first material, a second electrode made of a second material, and a first resistive switching film arranged between the first and second electrodes. The first resistive switching film is connected to both the first and second electrodes. The second memristor includes a third electrode made of a third material, a fourth electrode made of the second material, and a second resistive switching film arranged between the third and fourth electrodes. The second resistive switching film is connected to both the third and fourth electrodes. The work function of the first material is smaller than that of the second material. The work function of the third material is larger than that of the second material.
摘要翻译：根据实施例，半导体器件包括第一和第二忆阻器。第一忆阻器包括由第一材料制成的第一电极，由第二材料制成的第二电极和布置在第一和第二电极之间的第一电阻切换膜。第一电阻开关膜连接到第一和第二电极。第二忆阻器包括由第三材料制成的第三电极，由第二材料制成的第四电极和布置在第三和第四电极之间的第二电阻切换膜。第二电阻开关膜连接到第三和第四电极。第一材料的功函数小于第二材料的功函数。第三种材料的功函数大于第二种材料的功函数。

3. 发明申请

US20120117354A1 STORAGE DEVICE IN WHICH FORWARDING-FUNCTION-EQUIPPED MEMORY NODES ARE MUTUALLY CONNECTED AND DATA PROCESSING METHOD 有权
标题翻译：存储设备，其中前向功能的存储器端口被连接和数据处理方法
公开(公告)号：US20120117354A1
公开(公告)日：2012-05-10
申请号：US13293399
申请日：2011-11-10
申请人： Kosuke Tatsumura , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki , Yoshifumi Nishi , Takao Marukame , Takahiro Kurita
发明人： Kosuke Tatsumura , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki , Yoshifumi Nishi , Takao Marukame , Takahiro Kurita
IPC分类号： G06F12/02
CPC分类号： H04L49/253 , G06F3/0605 , G06F3/0635 , G06F3/0656 , G06F3/0658 , G06F3/0683 , H04L12/6418 , H04L45/74
摘要： According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
摘要翻译：根据一个实施例，存储设备包括多个存储器节点。每个存储器节点包括多个输入端口，多个输出端口，选择器，分组控制器和存储器。选择器将输入到输入端口的数据包输出输出到其中一个输出端口。分组控制器控制选择器。内存存储数据。存储器节点在输入端口和输出端口相互连接。存储器节点具有由其物理位置确定的地址。当接收到没有寻址到具有分组控制器的存储器节点的分组时，分组控制器基于包括分组的目的地地址的信息和具有分组控制器的存储器节点的地址来切换输出分组的输出端口。

4. 发明授权

US09246709B2 Storage device in which forwarding-function-equipped memory nodes are mutually connected and data processing method 有权
标题翻译：具有转发功能的存储器节点相互连接的存储设备和数据处理方法
公开(公告)号：US09246709B2
公开(公告)日：2016-01-26
申请号：US13293399
申请日：2011-11-10
申请人： Kosuke Tatsumura , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki , Yoshifumi Nishi , Takao Marukame , Takahiro Kurita
发明人： Kosuke Tatsumura , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki , Yoshifumi Nishi , Takao Marukame , Takahiro Kurita
IPC分类号： G06F12/02 , H04L12/64 , G06F3/06
CPC分类号： H04L49/253 , G06F3/0605 , G06F3/0635 , G06F3/0656 , G06F3/0658 , G06F3/0683 , H04L12/6418 , H04L45/74
摘要： According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
摘要翻译：根据一个实施例，存储设备包括多个存储器节点。每个存储器节点包括多个输入端口，多个输出端口，选择器，分组控制器和存储器。选择器将输入到输入端口的数据包输出输出到其中一个输出端口。分组控制器控制选择器。内存存储数据。存储器节点在输入端口和输出端口相互连接。存储器节点具有由其物理位置确定的地址。当接收到没有寻址到具有分组控制器的存储器节点的分组时，分组控制器基于包括分组的目的地地址的信息和具有分组控制器的存储器节点的地址来切换输出分组的输出端口。

5. 发明授权

US08618590B2 Spin transistor, integrated circuit, and magnetic memory 有权
标题翻译：旋转晶体管，集成电路和磁存储器
公开(公告)号：US08618590B2
公开(公告)日：2013-12-31
申请号：US12561475
申请日：2009-09-17
申请人： Tomoaki Inokuchi , Takao Marukame , Mizue Ishikawa , Hideyuki Sugiyama , Yoshiaki Saito
发明人： Tomoaki Inokuchi , Takao Marukame , Mizue Ishikawa , Hideyuki Sugiyama , Yoshiaki Saito
IPC分类号： H01L21/02 , G11C11/14
CPC分类号： H01L29/66984 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： A spin transistor includes a first ferromagnetic layer, a second ferromagnetic layer, a semiconductor layer between the first and second ferromagnetic layers, and a gate electrode on or above a surface of the semiconductor layer, the surface being between the first and second ferromagnetic layers. The first ferromagnetic layer comprises a ferromagnet which has a first minority spin band located at a high energy side and a second minority spin band located at a low energy side, and has a Fermi level in an area of the high energy side higher than a middle of a gap between the first and second minority spin bands.
摘要翻译：自旋晶体管包括第一铁磁层，第二铁磁层，第一和第二铁磁层之间的半导体层，以及在半导体层的表面上或上方的栅电极，该表面位于第一和第二铁磁层之间。第一铁磁层包括具有位于高能侧的第一少数自旋带和位于低能侧的第二少数自旋带的铁磁体，并且在高能量侧的区域中的费米能级高于中间第一和第二少数自旋带之间的间隙。

6. 发明申请

US20130252559A1 DA CONVERTER AND WIRELESS COMMUNICATION APPARATUS 有权
标题翻译： DA转换器和无线通信设备
公开(公告)号：US20130252559A1
公开(公告)日：2013-09-26
申请号：US13599413
申请日：2012-08-30
申请人： Jun DEGUCHI , Shouhei Kousai , Yousuke Hagiwara , Masamichi Suzuki , Atsuhiro Kinoshita , Takao Marukame
发明人： Jun DEGUCHI , Shouhei Kousai , Yousuke Hagiwara , Masamichi Suzuki , Atsuhiro Kinoshita , Takao Marukame
IPC分类号： H03M1/66
CPC分类号： H03M1/66 , H03M1/1061 , H03M1/745
摘要： In general, according to one embodiment, a DA converter configured to convert a digital signal comprising n (n>1) bits to an analog current to output the analog current from an output terminal, includes n voltage-current converters. Each of them corresponds to each bit of the digital signal and is configured to generate a current depending on the corresponding bit. A k-th (k is an integer of 0 to n−1) voltage-current converter includes a first transistor whose threshold voltage is adjustable. The first transistor includes a semiconductor substrate, a first diffusion region, a second diffusion region, an insulating film, a charge accumulating film, and a gate.
摘要翻译：通常，根据一个实施例，配置成将包括n（n> 1）位的数字信号转换为模拟电流以从输出端输出模拟电流的DA转换器包括n个电压 - 电流转换器。它们中的每一个对应于数字信号的每个位，并且被配置为根据相应的位产生电流。第k（k是0到n-1的整数）电压 - 电流转换器包括阈值电压可调的第一晶体管。第一晶体管包括半导体衬底，第一扩散区，第二扩散区，绝缘膜，电荷累积膜和栅极。

7. 发明授权

US08487359B2 Spin MOSFET and reconfigurable logic circuit using the spin MOSFET 有权
标题翻译：使用自旋MOSFET的Spin MOSFET和可重构逻辑电路
公开(公告)号：US08487359B2
公开(公告)日：2013-07-16
申请号：US12486999
申请日：2009-06-18
申请人： Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi , Mizue Ishikawa , Takao Marukame
发明人： Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi , Mizue Ishikawa , Takao Marukame
IPC分类号： H01L27/108
CPC分类号： H01L29/66984 , B82Y25/00 , H01F10/3272 , H01F10/3286
摘要： It is made possible to provide a spin MOSFET that can minimize the increase in production costs and can perform both spin injection writing and reading. A spin MOSFET includes: a substrate that has a semiconductor region of a first conductivity type; first and second ferromagnetic stacked films that are formed at a distance from each other on the semiconductor region, and each have the same stacked structure comprising a first ferromagnetic layer, a nonmagnetic layer, and a second ferromagnetic layer stacked in this order, the second ferromagnetic stacked film having a film-plane area different from that of the first ferromagnetic stacked film; a gate insulating film that is formed on a portion of the semiconductor region, the portion being located between the first ferromagnetic stacked film and the second ferromagnetic stacked film; and a gate that is formed on the gate insulating film.
摘要翻译：可以提供一种可以使生产成本增加最小化的自旋MOSFET，并且可以执行自动注入写入和读取两种操作。自旋MOSFET包括：具有第一导电类型的半导体区域的衬底; 第一和第二铁磁层叠膜，其形成在半导体区域上彼此间隔一定距离处，并且各自具有包括依次层叠的第一铁磁层，非磁性层和第二铁磁层的相同层叠结构，第二铁磁体具有与第一铁磁性层叠膜不同的膜面积的层叠膜; 形成在所述半导体区域的一部分上的所述栅绝缘膜，所述栅极绝缘膜位于所述第一铁磁层叠膜和所述第二铁磁性堆叠膜之间; 以及形成在栅极绝缘膜上的栅极。

8. 发明授权

US08330196B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08330196B2
公开(公告)日：2012-12-11
申请号：US13419947
申请日：2012-03-14
申请人： Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Hideyuki Sugiyama , Yoshiaki Saito
发明人： Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Hideyuki Sugiyama , Yoshiaki Saito
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66984 , H01L21/823814 , H01L21/84 , H01L21/845 , H01L29/41766 , H01L29/456 , H01L29/49 , H01L29/66075
摘要： A semiconductor device according to an embodiment includes: a semiconductor layer; source and drain regions in the semiconductor layer; a magnetic metal semiconductor compound film on each of the source and drain regions, the magnetic metal semiconductor compound film including the same semiconductor as a semiconductor of the semiconductor layer and a magnetic metal; a gate insulating film on the semiconductor layer between the source region and the drain region; a gate electrode on the gate insulating film; a gate sidewall formed at a side portion of the gate electrode, the gate sidewall being made of an insulating material; a film stack formed on the magnetic metal semiconductor compound film on each of the source and drain regions, the film stack including a magnetic layer; and an oxide layer formed on the gate sidewall, the oxide layer containing the same element as an element in the film stack.
摘要翻译：根据实施例的半导体器件包括：半导体层; 半导体层中的源极和漏极区域; 在源极和漏极区域中的每一个上的磁性金属半导体化合物膜，包括与半导体层的半导体相同的半导体的磁性金属半导体化合物膜和磁性金属; 源极区域和漏极区域之间的半导体层上的栅极绝缘膜; 栅极绝缘膜上的栅电极; 栅极侧壁，其形成在所述栅电极的侧部，所述栅极侧壁由绝缘材料制成; 在所述源极和漏极区域中的每一个上形成在所述磁性金属半导体化合物膜上的膜堆叠，所述膜堆叠包括磁性层; 以及形成在栅极侧壁上的氧化物层，所述氧化物层包含与膜堆叠中的元件相同的元件。

9. 发明授权

US08154916B2 Nonvolatile memory circuit using spin MOS transistors 有权
标题翻译：使用自旋MOS晶体管的非易失性存储电路
公开(公告)号：US08154916B2
公开(公告)日：2012-04-10
申请号：US12889881
申请日：2010-09-24
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： G11C11/14
CPC分类号： G11C14/0081
摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
摘要翻译：某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

10. 发明申请

US20120074984A1 LOOK-UP TABLE CIRCUITS AND FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：查看表电路和现场可编程门阵列
公开(公告)号：US20120074984A1
公开(公告)日：2012-03-29
申请号：US13238020
申请日：2011-09-21
申请人： Hideyuki SUGIYAMA , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki SUGIYAMA , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： H03K19/177 , H03K5/00
CPC分类号： H03K19/177
摘要： A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.
摘要翻译：根据实施例的查找表电路包括：可变电阻电路，包括可变电阻器件，并且基于输入信号从可变电阻器件中选择可变电阻器件; 参考电路，其具有可变电阻电路的最大电阻值和最小电阻值之间的电阻值; 第一n沟道MOSFET，其包括连接到可变电阻电路的端子的源极和连接到漏极的栅极; 第二n沟道MOSFET，其包括连接到参考电路的端子的源极和连接到第一n沟道MOSFET的栅极的栅极; 用于向可变电阻电路提供电流的第一电流供应电路; 第二电流供应电路，用于向参考电路提供电流; 以及比较器，用于比较第一输入端和第二输入端的电压。

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