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1. 发明申请

US20070188194A1 Level shifter circuit and method thereof 审中-公开
标题翻译：电平移位电路及其方法
公开(公告)号：US20070188194A1
公开(公告)日：2007-08-16
申请号：US11700907
申请日：2007-02-01
申请人： Hui-kap Yang , Young-gu Kang , Ki-chul Chun , Eun-sung Seo , Mi-jo Kim
发明人： Hui-kap Yang , Young-gu Kang , Ki-chul Chun , Eun-sung Seo , Mi-jo Kim
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528
摘要： A level shifter circuit and method thereof are provided. The example level shifter circuit may include a pull-up drive unit driving an output node from a first voltage to a second voltage in response to an input signal, a target voltage for the second voltage higher than a target voltage for the first voltage and the input signal based on the first voltage and a third voltage and a pull-down drive unit driving the output node to the third voltage in response to the input signal, the pull-up and pull-down drive units adjusting current levels of at least one of a pull-up current flowing through the pull-up drive unit and a pull-down current flowing through the pull-down drive unit based on whether the pull-up drive unit and the pull-down drive unit are operating concurrently. The example method may include pull-up driving an output node from a first voltage to a second voltage in response to an input signal, a target voltage for the second voltage higher than a target voltage for the first voltage and the input signal based on the first voltage and a third voltage, pull-down driving the output node to the third voltage in response to the input signal, determining whether the pull-up and pull-down driving operations are performed concurrently and adjusting current levels of at least one of a pull-up current and a pull-down current based on the determining step.
摘要翻译：提供了一种电平移位器电路及其方法。示例电平移位器电路可以包括上拉驱动单元，其响应于输入信号将输出节点从第一电压驱动到第二电压，第二电压的目标电压高于第一电压的目标电压，基于所述第一电压的输入信号和第三电压和下拉驱动单元，所述下拉驱动单元响应于所述输入信号将所述输出节点驱动到所述第三电压，所述上拉和下拉驱动单元调整至少一个基于上拉驱动单元和下拉驱动单元是否同时工作，流过上拉驱动单元的上拉电流和流经下拉驱动单元的下拉电流。示例性方法可以包括响应于输入信号将输出节点从第一电压驱动到第二电压的上拉，用于第二电压的目标电压高于第一电压的目标电压，以及基于第一电压和第三电压，响应于输入信号将输出节点下拉驱动到第三电压，确定是否同时执行上拉和下拉驱动操作，并且调整以下中的至少一个的电流水平基于确定步骤的上拉电流和下拉电流。

2. 发明授权

US07230475B2 Semiconductor devices including an external power voltage control function and methods of operating the same 失效
标题翻译：包括外部电源电压控制功能的半导体器件及其操作方法
公开(公告)号：US07230475B2
公开(公告)日：2007-06-12
申请号：US11005523
申请日：2004-12-06
申请人： Jong-Hyun Choi , Mi-Jo Kim , Kwang-Sook Noh , Beob-Rae Cho
发明人： Jong-Hyun Choi , Mi-Jo Kim , Kwang-Sook Noh , Beob-Rae Cho
IPC分类号： G05F1/10
CPC分类号： G11C11/4074 , G11C5/143 , G11C7/20 , G11C2207/2227
摘要： A semiconductor device includes a memory and a power voltage interrupter configured to interrupt an external power voltage applied to circuitry of the semiconductor device responsive to a Deep Power Down (DPD) command signal generated in a DPD mode of the memory. A power voltage shifter is configured to shift a power voltage in the circuitry to a specific level responsive to the DPD command signal.
摘要翻译：半导体器件包括存储器和电源电压中断器，其被配置为响应于在存储器的DPD模式中产生的深度掉电（DPD）命令信号来中断施加到半导体器件的电路的外部电源电压。电源电压移位器被配置为响应于DPD命令信号将电路中的电源电压移动到特定电平。

3. 发明授权

US08131897B2 Semiconductor memory device inputting and outputting a plurality of data length formats and method thereof 失效
标题翻译：半导体存储器件输入和输出多种数据长度格式及其方法
公开(公告)号：US08131897B2
公开(公告)日：2012-03-06
申请号：US11806585
申请日：2007-06-01
申请人： Soo-Young Kim , Mi-Jo Kim , Jung-Soo Ryoo
发明人： Soo-Young Kim , Mi-Jo Kim , Jung-Soo Ryoo
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F13/1663 , G06F15/167 , G11C7/10 , G11C7/1006 , G11C7/1012 , G11C7/1045
摘要： A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a first processor configured to exchange data with a first data length format, a second processor configured to exchange data with a second data length format and a shared memory configured to store data, the shared memory being shared by the first and second processors, the shared memory further configured to receive a read command from at least one of the first and second processors and to output data in response to the read command based on which of the first and second data length formats is used by the processor issuing the read command.
摘要翻译：提供一种半导体存储器件及其方法。示例性半导体存储器件可以包括被配置为与第一数据长度格式交换数据的第一处理器，被配置为与第二数据长度格式交换数据的第二处理器和被配置为存储数据的共享存储器，共享存储器由第一和第二处理器，共享存储器还被配置为从第一和第二处理器中的至少一个接收读取命令，并响应于读取命令输出数据，该命令基于第一和第二数据长度格式中的哪一个被处理器发出读命令。

4. 发明授权

US07420831B2 Semiconductor chip and semiconductor chip package comprising semiconductor chip 失效
标题翻译：包括半导体芯片的半导体芯片和半导体芯片封装
公开(公告)号：US07420831B2
公开(公告)日：2008-09-02
申请号：US11702092
申请日：2007-02-05
申请人： Eun-sung Seo , Mi-jo Kim , Soo-young Kim
发明人： Eun-sung Seo , Mi-jo Kim , Soo-young Kim
IPC分类号： G11C5/06
CPC分类号： G11C5/066 , G11C5/04 , G11C8/06 , G11C8/12 , G11C11/40615 , G11C29/1201 , G11C29/48
摘要： Embodiments of the invention provide a semiconductor chip and a semiconductor chip package comprising a semiconductor chip. In one embodiment, the invention provides a semiconductor chip comprising a memory cell array, a control circuit, and a chip selection signal generating circuit electrically connected to first and second option pads. In the semiconductor chip, the chip selection signal generating circuit is enabled in accordance with a dual chip enable signal, and the control circuit is enabled and disabled in accordance with the chip selection signal received from the chip selection signal generating circuit. In addition, the chip selection signal generating circuit is adapted to generate a chip selection signal in accordance with signals received through the first and second option pads, respectively.
摘要翻译：本发明的实施例提供一种半导体芯片和包括半导体芯片的半导体芯片封装。在一个实施例中，本发明提供一种半导体芯片，其包括电连接到第一和第二选择焊盘的存储单元阵列，控制电路和芯片选择信号发生电路。在半导体芯片中，芯片选择信号发生电路根据双芯片使能信号使能，并且控制电路根据从芯片选择信号发生电路接收的芯片选择信号而被使能和禁止。此外，芯片选择信号发生电路适于分别根据通过第一和第二可选焊盘接收的信号产生芯片选择信号。

5. 发明申请

US20050122820A1 Semiconductor devices including an external power voltage control function and methods of operating the same 失效
标题翻译：包括外部电源电压控制功能的半导体器件及其操作方法
公开(公告)号：US20050122820A1
公开(公告)日：2005-06-09
申请号：US11005523
申请日：2004-12-06
申请人： Jong-Hyun Choi , Mi-Jo Kim , Kwang-Sook Noh , Beob-Rae Cho
发明人： Jong-Hyun Choi , Mi-Jo Kim , Kwang-Sook Noh , Beob-Rae Cho
IPC分类号： G11C5/14 , G11C7/00 , G11C7/20 , G11C11/4074
CPC分类号： G11C11/4074 , G11C5/143 , G11C7/20 , G11C2207/2227
摘要： A semiconductor device includes a memory and a power voltage interrupter configured to interrupt an external power voltage applied to circuitry of the semiconductor device responsive to a Deep Power Down (DPD) command signal generated in a DPD mode of the memory. A power voltage shifter is configured to shift a power voltage in the circuitry to a specific level responsive to the DPD command signal.
摘要翻译：半导体器件包括存储器和电源电压中断器，其被配置为响应于在存储器的DPD模式中产生的深度掉电（DPD）命令信号来中断施加到半导体器件的电路的外部电源电压。电源电压移位器被配置为响应于DPD命令信号将电路中的电源电压移动到特定电平。

6. 发明申请

US20080126604A1 Semiconductor memory device and method thereof 失效
标题翻译：半导体存储器件及其方法
公开(公告)号：US20080126604A1
公开(公告)日：2008-05-29
申请号：US11806585
申请日：2007-06-01
申请人： Soo-Young Kim , Mi-Jo Kim , Jung-Soo Ryoo
发明人： Soo-Young Kim , Mi-Jo Kim , Jung-Soo Ryoo
IPC分类号： G06F13/28
CPC分类号： G06F13/1663 , G06F15/167 , G11C7/10 , G11C7/1006 , G11C7/1012 , G11C7/1045
摘要： A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a first processor configured to exchange data with a first data length format, a second processor configured to exchange data with a second data length format and a shared memory configured to store data, the shared memory being shared by the first and second processors, the shared memory further configured to receive a read command from at least one of the first and second processors and to output data in response to the read command based on which of the first and second data length formats is used by the processor issuing the read command.
摘要翻译：提供一种半导体存储器件及其方法。示例性半导体存储器件可以包括被配置为与第一数据长度格式交换数据的第一处理器，被配置为与第二数据长度格式交换数据的第二处理器和被配置为存储数据的共享存储器，共享存储器由第一和第二处理器，共享存储器还被配置为从第一和第二处理器中的至少一个接收读取命令，并响应于读取命令输出数据，该命令基于第一和第二数据长度格式中的哪一个被处理器发出读命令。

7. 发明申请

US20080077937A1 MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE WITH HOST INTERFACE BETWEEN PROCESSORS 有权
标题翻译：具有处理器之间主机接口的多路可访问半导体存储器件
公开(公告)号：US20080077937A1
公开(公告)日：2008-03-27
申请号：US11829859
申请日：2007-07-27
申请人： Yun-Hee SHIN , Han-Gu SOHN , Young-Min LEE , Dong-Hyuk LEE , Jong-Wook PARK , Ho-Cheol LEE , Mi-Jo KIM , Jung-Sik KIM , Chang-Ho LEE
发明人： Yun-Hee SHIN , Han-Gu SOHN , Young-Min LEE , Dong-Hyuk LEE , Jong-Wook PARK , Ho-Cheol LEE , Mi-Jo KIM , Jung-Sik KIM , Chang-Ho LEE
IPC分类号： G06F15/167 , G06F9/30
CPC分类号： G11C7/1075 , G11C7/1012 , G11C11/4096
摘要： A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.
摘要翻译：多路可及半导体存储器件提供处理器之间的接口功能。存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

8. 发明授权

US07941612B2 Multipath accessible semiconductor memory device with host interface between processors 有权
标题翻译：多路径可访问的半导体存储器件，具有处理器之间的主机接口
公开(公告)号：US07941612B2
公开(公告)日：2011-05-10
申请号：US11829859
申请日：2007-07-27
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Dong-Hyuk Lee , Jong-Wook Park , Ho-Cheol Lee , Mi-Jo Kim , Jung-Sik Kim , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Dong-Hyuk Lee , Jong-Wook Park , Ho-Cheol Lee , Mi-Jo Kim , Jung-Sik Kim , Chang-Ho Lee
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C7/1012 , G11C11/4096
摘要： A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.
摘要翻译：多路可及半导体存储器件提供处理器之间的接口功能。存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

9. 发明申请

US20070189050A1 Semiconductor chip and semiconductor chip package comprising semiconductor chip 失效
标题翻译：包括半导体芯片的半导体芯片和半导体芯片封装
公开(公告)号：US20070189050A1
公开(公告)日：2007-08-16
申请号：US11702092
申请日：2007-02-05
申请人： Eun-sung Seo , Mi-jo Kim , Soo-young Kim
发明人： Eun-sung Seo , Mi-jo Kim , Soo-young Kim
IPC分类号： G11C5/06
CPC分类号： G11C5/066 , G11C5/04 , G11C8/06 , G11C8/12 , G11C11/40615 , G11C29/1201 , G11C29/48
摘要： Embodiments of the invention provide a semiconductor chip and a semiconductor chip package comprising a semiconductor chip. In one embodiment, the invention provides a semiconductor chip comprising a memory cell array, a control circuit, and a chip selection signal generating circuit electrically connected to first and second option pads. In the semiconductor chip, the chip selection signal generating circuit is enabled in accordance with a dual chip enable signal, and the control circuit is enabled and disabled in accordance with the chip selection signal received from the chip selection signal generating circuit. In addition, the chip selection signal generating circuit is adapted to generate a chip selection signal in accordance with signals received through the first and second option pads, respectively.
摘要翻译：本发明的实施例提供一种半导体芯片和包括半导体芯片的半导体芯片封装。在一个实施例中，本发明提供一种半导体芯片，其包括电连接到第一和第二选择焊盘的存储单元阵列，控制电路和芯片选择信号发生电路。在半导体芯片中，芯片选择信号发生电路根据双芯片使能信号使能，并且控制电路根据从芯片选择信号发生电路接收的芯片选择信号而被使能和禁止。此外，芯片选择信号发生电路适于分别根据通过第一和第二可选焊盘接收的信号产生芯片选择信号。

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