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1. 发明授权

US07941612B2 Multipath accessible semiconductor memory device with host interface between processors 有权
标题翻译：多路径可访问的半导体存储器件，具有处理器之间的主机接口
公开(公告)号：US07941612B2
公开(公告)日：2011-05-10
申请号：US11829859
申请日：2007-07-27
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Dong-Hyuk Lee , Jong-Wook Park , Ho-Cheol Lee , Mi-Jo Kim , Jung-Sik Kim , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Dong-Hyuk Lee , Jong-Wook Park , Ho-Cheol Lee , Mi-Jo Kim , Jung-Sik Kim , Chang-Ho Lee
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C7/1012 , G11C11/4096
摘要： A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.
摘要翻译：多路可及半导体存储器件提供处理器之间的接口功能。存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

2. 发明授权

US07870326B2 Multiprocessor system and method thereof 有权
标题翻译：多处理器系统及其方法
公开(公告)号：US07870326B2
公开(公告)日：2011-01-11
申请号：US11819601
申请日：2007-06-28
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
IPC分类号： G06F12/00
CPC分类号： G06F12/02
摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.
摘要翻译：提供了一种多处理器系统及其方法。示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址，通过第二个端口，银行地址选择第四个存储器，作为与银行地址相同的银行地址，选择第三个存储器银行通过第一个港口。

3. 发明申请

US20110107006A1 Multiprocessor system and method thereof 审中-公开
公开(公告)号：US20110107006A1
公开(公告)日：2011-05-05
申请号：US12929222
申请日：2011-01-10
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
IPC分类号： G06F12/00
CPC分类号： G06F12/02
摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

4. 发明申请

US20080172516A1 Multiprocessor system and method thereof 有权
标题翻译：多处理器系统及其方法
公开(公告)号：US20080172516A1
公开(公告)日：2008-07-17
申请号：US11819601
申请日：2007-06-28
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
IPC分类号： G06F12/02
CPC分类号： G06F12/02
摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.
摘要翻译：提供了一种多处理器系统及其方法。示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址，通过第二个端口，银行地址选择第四个存储器，作为银行地址作为银行地址，选择第三个存储器银行通过第一个港口。

5. 发明授权

US08122199B2 Multi port memory device with shared memory area using latch type memory cells and driving method 失效
标题翻译：具有共享存储区域的多端口存储器件使用锁存型存储单元和驱动方法
公开(公告)号：US08122199B2
公开(公告)日：2012-02-21
申请号：US12392432
申请日：2009-02-25
申请人： Jin-Hyoung Kwon , Kyung-Woo Nam , Han-Gu Sohn , Ho-Cheol Lee , Kwang-Myeong Jang
发明人： Jin-Hyoung Kwon , Kyung-Woo Nam , Han-Gu Sohn , Ho-Cheol Lee , Kwang-Myeong Jang
IPC分类号： G06F12/00
CPC分类号： G11C11/413 , G11C7/1075
摘要： A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.
摘要翻译：多端口半导体存储器件包括：分别耦合到第一和第二处理器的第一和第二端口单元，分别由第一和第二处理器访问的第一和第二专用存储器区域，并且使用DRAM单元实现;第一和第二处理器通过相应的第一和第二处理器共同访问的共享存储器区域端口单元，并且使用与实现第一和第二专用存储区域的DRAM单元不同的存储器单元来实现，以及端口连接控制单元，其控制共享存储区域与第一和第二端口单元之间的数据路径配置，以使得第一和第二个处理器通过共享内存区域。

6. 发明申请

US20110093235A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110093235A1
公开(公告)日：2011-04-21
申请号：US12900547
申请日：2010-10-08
申请人： CHI-SUNG OH , Dong-Hyuk Lee , Ho-Cheol Lee , Jang-Woo Ryu , Jung-Bae Lee
发明人： CHI-SUNG OH , Dong-Hyuk Lee , Ho-Cheol Lee , Jang-Woo Ryu , Jung-Bae Lee
IPC分类号： G01R31/14 , H03L7/00
CPC分类号： G01R31/2884 , G01R31/31726
摘要： A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.
摘要翻译：提供半导体器件。半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

7. 发明授权

US08396682B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08396682B2
公开(公告)日：2013-03-12
申请号：US12900547
申请日：2010-10-08
申请人： Chi-Sung Oh , Dong-Hyuk Lee , Ho-Cheol Lee , Jang-Woo Ryu , Jung-Bae Lee
发明人： Chi-Sung Oh , Dong-Hyuk Lee , Ho-Cheol Lee , Jang-Woo Ryu , Jung-Bae Lee
IPC分类号： G01R27/28 , G06F19/00
CPC分类号： G01R31/2884 , G01R31/31726
摘要： A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.
摘要翻译：提供半导体器件。半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

8. 发明授权

US08625381B2 Stacked semiconductor device 有权
标题翻译：堆叠半导体器件
公开(公告)号：US08625381B2
公开(公告)日：2014-01-07
申请号：US13026460
申请日：2011-02-14
申请人： Ho-Cheol Lee
发明人： Ho-Cheol Lee
IPC分类号： G11C5/06 , G11C5/02 , H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40 , H01L21/00 , G11C8/02 , G11C8/12 , G11C8/10
CPC分类号： H01L23/544 , H01L24/04 , H01L24/16 , H01L25/0657 , H01L25/18 , H01L2223/54433 , H01L2223/5444 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0002 , H01L2924/01019 , H01L2924/01055 , H01L2924/14 , H01L2924/15311 , H01L2224/05552
摘要： Provided is a stacked semiconductor device including n stacked chips. Each chip includes “j” corresponding upper and lower electrodes, wherein j is a minimal natural number greater than or equal to n/2, and an identification code generator including a single inverter connecting one of the j first upper electrode to a corresponding one of the j lower electrodes. The upper electrodes receive a previous identification code, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code. The current identification code is applied through the j lower electrodes and corresponding TSVs to communicate the current identification code to the upper adjacent chip.
摘要翻译：提供了包括n个堆叠芯片的堆叠半导体器件。每个芯片包括对应的上部和下部电极的“j”，其中j是大于或等于n / 2的最小自然数，以及识别码发生器，其包括将j个第一上电极中的一个连接到 j个下电极。上电极接收先前的识别码，以1位为单位旋转先前的识别码，并且反转已转动的先前识别码的1位，以产生当前识别码。通过j个下部电极和相应的TSV施加当前的识别码，以将当前识别码传送到上部相邻的芯片。

9. 发明申请

US20080205175A1 Auto-precharge control circuit in semiconductor memory and method thereof 审中-公开
标题翻译：半导体存储器中的自动预充电控制电路及其方法
公开(公告)号：US20080205175A1
公开(公告)日：2008-08-28
申请号：US12068280
申请日：2008-02-05
申请人： Sang-Kyun Park , Ho-Cheol Lee
发明人： Sang-Kyun Park , Ho-Cheol Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/1072 , G11C7/12 , G11C7/22 , G11C11/4094 , G11C2207/229
摘要： An auto-precharge control circuit in a semiconductor memory and method thereof, where the auto-precharge starting point may vary. The auto-precharge starting point may vary in response to at least one control signal. The auto-precharge starting point may vary in accordance with frequency and/or latency information. The auto-precharge starting point may vary in response to at least one control signal including clock frequency information. The auto-precharge starting point may vary depending on a latency signal received from a mode register setting command. The auto-precharge control circuit may include a control circuit for receiving a write signal, a clock signal and at least one control signal, including at least one of clock frequency information and latency information, and outputting at least one path signal; an auto-precharge pulse signal driver for receiving the at least one path signal, the write signal, and an enable signal and producing an auto-precharge pulse signal, the auto-precharge pulse signal identifying a starting point for an auto-precharge operation; and an auto-precharge mode enabling circuit for receiving the clock signal, an auto-precharge command, an active signal, and the auto-precharge pulse signal and generating the enable signal.
摘要翻译：半导体存储器中的自动预充电控制电路及其方法，其中自动预充电起点可以变化。自动预充电起始点可以响应于至少一个控制信号而变化。自动预充电起始点可以根据频率和/或延迟信息而变化。响应于包括时钟频率信息的至少一个控制信号，自动预充电起始点可以变化。自动预充电起点可以根据从模式寄存器设置命令接收到的等待时间信号而变化。自动预充电控制电路可以包括用于接收包括时钟频率信息和等待时间信息中的至少一个的写入信号，时钟信号和至少一个控制信号的控制电路，并且输出至少一个路径信号; 自动预充电脉冲信号驱动器，用于接收至少一个路径信号，写入信号和使能信号，并产生自动预充电脉冲信号，所述自动预充电脉冲信号标识自动预充电操作的起始点; 以及自动预充电模式使能电路，用于接收时钟信号，自动预充电命令，有效信号和自动预充电脉冲信号，并产生使能信号。

10. 发明授权

US06928023B2 Apparatus for and method of controlling AIVC through block selection information in semiconductor memory device 有权
标题翻译：用于通过半导体存储器件中的块选择信息来控制AIVC的装置和方法
公开(公告)号：US06928023B2
公开(公告)日：2005-08-09
申请号：US10465553
申请日：2003-06-20
申请人： Ho-Cheol Lee , Jung-Soo Ryoo
发明人： Ho-Cheol Lee , Jung-Soo Ryoo
IPC分类号： G11C7/00 , G11C5/06 , G11C5/14 , G11C8/12
CPC分类号： G11C5/063 , G11C5/14 , G11C8/12
摘要： A method of controlling a bank voltage (AIVC) through memory block selection information, said method comprising the steps of detecting an array block selection signal of an array block disposed distantly from an AIVC driver in response to an activated memory array block selection signal; and supplying a second bank voltage to a memory bank by driving a normal size driver and an oversize driver when detecting the array block selection signal for the distantly disposed array block.
摘要翻译：一种通过存储块选择信息控制存储体电压（AIVC）的方法，所述方法包括以下步骤：响应激活的存储器阵列块选择信号，检测远离AIVC驱动器的阵列块的阵列块选择信号; 以及当检测到用于远处布置的阵列块的阵列块选择信号时，通过驱动正常尺寸的驱动器和超大驱动器，将第二存储体电压提供给存储体。

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