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1. 发明授权

US07941612B2 Multipath accessible semiconductor memory device with host interface between processors 有权
标题翻译：多路径可访问的半导体存储器件，具有处理器之间的主机接口
公开(公告)号：US07941612B2
公开(公告)日：2011-05-10
申请号：US11829859
申请日：2007-07-27
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Dong-Hyuk Lee , Jong-Wook Park , Ho-Cheol Lee , Mi-Jo Kim , Jung-Sik Kim , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Dong-Hyuk Lee , Jong-Wook Park , Ho-Cheol Lee , Mi-Jo Kim , Jung-Sik Kim , Chang-Ho Lee
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C7/1012 , G11C11/4096
摘要： A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.
摘要翻译：多路可及半导体存储器件提供处理器之间的接口功能。存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

2. 发明申请

US20080172516A1 Multiprocessor system and method thereof 有权
标题翻译：多处理器系统及其方法
公开(公告)号：US20080172516A1
公开(公告)日：2008-07-17
申请号：US11819601
申请日：2007-06-28
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
IPC分类号： G06F12/02
CPC分类号： G06F12/02
摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.
摘要翻译：提供了一种多处理器系统及其方法。示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址，通过第二个端口，银行地址选择第四个存储器，作为银行地址作为银行地址，选择第三个存储器银行通过第一个港口。

3. 发明授权

US07870326B2 Multiprocessor system and method thereof 有权
标题翻译：多处理器系统及其方法
公开(公告)号：US07870326B2
公开(公告)日：2011-01-11
申请号：US11819601
申请日：2007-06-28
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
IPC分类号： G06F12/00
CPC分类号： G06F12/02
摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.
摘要翻译：提供了一种多处理器系统及其方法。示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址，通过第二个端口，银行地址选择第四个存储器，作为与银行地址相同的银行地址，选择第三个存储器银行通过第一个港口。

4. 发明申请

US20110107006A1 Multiprocessor system and method thereof 审中-公开
公开(公告)号：US20110107006A1
公开(公告)日：2011-05-05
申请号：US12929222
申请日：2011-01-10
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
IPC分类号： G06F12/00
CPC分类号： G06F12/02
摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

5. 发明申请

US20090106503A1 Method, device, and system for preventing refresh starvation in shared memory bank 有权
标题翻译：用于防止共享存储器中刷新不足的方法，设备和系统
公开(公告)号：US20090106503A1
公开(公告)日：2009-04-23
申请号：US11977047
申请日：2007-10-23
申请人： Dong-Hyuk Lee , Kyung-Woo Nam , Yong-Jun Kim , Jong-Wook Park , Chi-Sung Oh
发明人： Dong-Hyuk Lee , Kyung-Woo Nam , Yong-Jun Kim , Jong-Wook Park , Chi-Sung Oh
IPC分类号： G06F12/14
CPC分类号： G11C11/406 , G11C7/1075 , G11C11/40603 , G11C11/40618
摘要： A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.
摘要翻译：多端口存储器件包括刷新寄存器和刷新控制器，用于防止存储器件的共享存储器单元中的刷新不足。存储装置还包括共享对共享存储器单元的访问的多个端口。刷新寄存器存储关于至少一个刷新命令的信息。刷新控制器根据存储在刷新寄存器中的信息来确定是否在端口权限转换时激活内部刷新操作。

6. 发明授权

US08166238B2 Method, device, and system for preventing refresh starvation in shared memory bank 有权
标题翻译：用于防止共享存储器中刷新不足的方法，设备和系统
公开(公告)号：US08166238B2
公开(公告)日：2012-04-24
申请号：US11977047
申请日：2007-10-23
申请人： Dong-Hyuk Lee , Kyung-Woo Nam , Yong-Jun Kim , Jong-Wook Park , Chi-Sung Oh
发明人： Dong-Hyuk Lee , Kyung-Woo Nam , Yong-Jun Kim , Jong-Wook Park , Chi-Sung Oh
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C7/1075 , G11C11/40603 , G11C11/40618
摘要： A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.
摘要翻译：多端口存储器件包括刷新寄存器和刷新控制器，用于防止存储器件的共享存储器单元中的刷新不足。存储装置还包括共享对共享存储器单元的访问的多个端口。刷新寄存器存储关于至少一个刷新命令的信息。刷新控制器根据存储在刷新寄存器中的信息来确定是否在端口权限转换时激活内部刷新操作。

7. 发明申请

US20110093235A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110093235A1
公开(公告)日：2011-04-21
申请号：US12900547
申请日：2010-10-08
申请人： CHI-SUNG OH , Dong-Hyuk Lee , Ho-Cheol Lee , Jang-Woo Ryu , Jung-Bae Lee
发明人： CHI-SUNG OH , Dong-Hyuk Lee , Ho-Cheol Lee , Jang-Woo Ryu , Jung-Bae Lee
IPC分类号： G01R31/14 , H03L7/00
CPC分类号： G01R31/2884 , G01R31/31726
摘要： A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.
摘要翻译：提供半导体器件。半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

8. 发明授权

US08396682B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08396682B2
公开(公告)日：2013-03-12
申请号：US12900547
申请日：2010-10-08
申请人： Chi-Sung Oh , Dong-Hyuk Lee , Ho-Cheol Lee , Jang-Woo Ryu , Jung-Bae Lee
发明人： Chi-Sung Oh , Dong-Hyuk Lee , Ho-Cheol Lee , Jang-Woo Ryu , Jung-Bae Lee
IPC分类号： G01R27/28 , G06F19/00
CPC分类号： G01R31/2884 , G01R31/31726
摘要： A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.
摘要翻译：提供半导体器件。半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

9. 发明申请

US20120126840A1 Semiconductor Device with Cross-shaped Bumps and Test Pads Alignment 审中-公开
标题翻译：具有十字形碰撞的半导体器件和测试焊盘对准
公开(公告)号：US20120126840A1
公开(公告)日：2012-05-24
申请号：US13240738
申请日：2011-09-22
申请人： Dong-Hyuk Lee , Chi-Sung Oh
发明人： Dong-Hyuk Lee , Chi-Sung Oh
IPC分类号： G01R31/3187
CPC分类号： G11C29/48 , G11C29/1201 , H01L22/32 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/50 , H01L2224/0346 , H01L2224/0362 , H01L2224/0401 , H01L2224/0557 , H01L2224/1146 , H01L2224/11622 , H01L2224/13005 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/14136 , H01L2224/16146 , H01L2224/16225 , H01L2224/81193 , H01L2224/81815 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01055 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/13099 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate; bumps disposed in a plurality of rows along a first axis direction of the semiconductor substrate; and test pads disposed in one or more columns along a second axis direction perpendicular to the first axis direction. The bumps and the test pads form a cross shape in the center portion of the semiconductor substrate. Disposing bumps in the central portion of the semiconductor substrate facilitates forming physical connections between stacked semiconductor devices of a semiconductor stack, regardless of the chip sizes.
摘要翻译：半导体器件包括半导体衬底; 沿着半导体衬底的第一轴线方向设置成多行的凸块; 以及沿着垂直于第一轴线方向的第二轴线方向设置在一个或多个列中的测试焊盘。凸块和测试焊盘在半导体衬底的中心部分形成十字形。在半导体衬底的中心部分设置凸起有助于在半导体堆叠的堆叠半导体器件之间形成物理连接，而与芯片尺寸无关。

10. 发明申请

US20110202918A1 VIRTUALIZATION APPARATUS FOR PROVIDING A TRANSACTIONAL INPUT/OUTPUT INTERFACE 审中-公开
标题翻译：用于提供交互式输入/输出接口的虚拟化设备
公开(公告)号：US20110202918A1
公开(公告)日：2011-08-18
申请号：US12985926
申请日：2011-01-06
申请人： Chan-Ju Park , Sang-Bum Suh , Dong-Hyuk Lee
发明人： Chan-Ju Park , Sang-Bum Suh , Dong-Hyuk Lee
IPC分类号： G06F9/455
CPC分类号： G06F9/45541
摘要： A virtualization apparatus and method for providing a transactional input/output interface to prevent input/output performance from deteriorating are provided. The virtualization apparatus includes hardware, a virtual machine monitor to support a plurality of operating systems to use the hardware, and a transaction device driver that executes transactions for hardware I/O operation and to provide an interface for executing a transaction for input/output operations to/from the hardware.
摘要翻译：提供一种用于提供事务输入/输出接口以防止输入/输出性能恶化的虚拟化装置和方法。虚拟化装置包括硬件，支持多个操作系统以使用硬件的虚拟机监视器以及执行用于硬件I / O操作的事务的事务设备驱动器，并提供用于执行用于输入/输出操作的事务的接口去/从硬件。

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