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1. 发明授权

US07941612B2 Multipath accessible semiconductor memory device with host interface between processors 有权
标题翻译：多路径可访问的半导体存储器件，具有处理器之间的主机接口
公开(公告)号：US07941612B2
公开(公告)日：2011-05-10
申请号：US11829859
申请日：2007-07-27
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Dong-Hyuk Lee , Jong-Wook Park , Ho-Cheol Lee , Mi-Jo Kim , Jung-Sik Kim , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Dong-Hyuk Lee , Jong-Wook Park , Ho-Cheol Lee , Mi-Jo Kim , Jung-Sik Kim , Chang-Ho Lee
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C7/1012 , G11C11/4096
摘要： A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.
摘要翻译：多路可及半导体存储器件提供处理器之间的接口功能。存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

2. 发明授权

US07870326B2 Multiprocessor system and method thereof 有权
标题翻译：多处理器系统及其方法
公开(公告)号：US07870326B2
公开(公告)日：2011-01-11
申请号：US11819601
申请日：2007-06-28
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
IPC分类号： G06F12/00
CPC分类号： G06F12/02
摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.
摘要翻译：提供了一种多处理器系统及其方法。示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址，通过第二个端口，银行地址选择第四个存储器，作为与银行地址相同的银行地址，选择第三个存储器银行通过第一个港口。

3. 发明申请

US20110107006A1 Multiprocessor system and method thereof 审中-公开
公开(公告)号：US20110107006A1
公开(公告)日：2011-05-05
申请号：US12929222
申请日：2011-01-10
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
IPC分类号： G06F12/00
CPC分类号： G06F12/02
摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

4. 发明申请

US20080172516A1 Multiprocessor system and method thereof 有权
标题翻译：多处理器系统及其方法
公开(公告)号：US20080172516A1
公开(公告)日：2008-07-17
申请号：US11819601
申请日：2007-06-28
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
IPC分类号： G06F12/02
CPC分类号： G06F12/02
摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.
摘要翻译：提供了一种多处理器系统及其方法。示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址，通过第二个端口，银行地址选择第四个存储器，作为银行地址作为银行地址，选择第三个存储器银行通过第一个港口。

5. 发明授权

US08209527B2 Memory system and memory management method including the same 有权
标题翻译：内存系统和内存管理方法包括相同
公开(公告)号：US08209527B2
公开(公告)日：2012-06-26
申请号：US12430722
申请日：2009-04-27
申请人： Jeon-Taek Im , Young-Min Lee , Han-Gu Sohn , Jin-Hyoung Kwon , Sung-Jae Byun , Yun-Tae Lee , Gyoo-Cheol Hwang
发明人： Jeon-Taek Im , Young-Min Lee , Han-Gu Sohn , Jin-Hyoung Kwon , Sung-Jae Byun , Yun-Tae Lee , Gyoo-Cheol Hwang
IPC分类号： G06F15/177
CPC分类号： G06F12/0607 , G06F9/4405 , G06F9/445 , G06F12/0638 , G06F15/177 , G06F2212/2022 , G11C8/16
摘要： A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.
摘要翻译：提供了具有第一处理器和第二处理器的数字处理的启动方法。第一处理器和外部之间的接口被停止。第二处理器程序代码从第一存储器发送到第二存储器。用于第一处理器的第二级装载器（SSL）从第一存储器发送到第二处理器的缓冲器。第一处理器程序代码在第二处理器的控制下从第一存储器发送到第二存储器，并且恢复第一处理器和外部之间的接口。第一处理器程序代码被快速下载到第二个存储器中以减少数字处理系统的引导时间。

6. 发明申请

US20100153637A1 Arbitration for memory device with commands 有权
公开(公告)号：US20100153637A1
公开(公告)日：2010-06-17
申请号：US12658911
申请日：2010-02-17
申请人： Young-Min Lee , Sung-Jae Byun , Han-Gu Sohn , Gyoo-Cheol Hwang
发明人： Young-Min Lee , Sung-Jae Byun , Han-Gu Sohn , Gyoo-Cheol Hwang
IPC分类号： G06F12/00 , G06F13/14
CPC分类号： G11C8/16 , G11C7/1075 , G11C11/406 , G11C11/40603 , G11C11/40611
摘要： A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS and PALL commands, for prevention of collision of commands, refresh starvation, and/or a missing pre-charge operation in the shared memory device.

7. 发明授权

US08711652B2 Arbitration for memory device with commands 有权
标题翻译：带指令的内存设备仲裁
公开(公告)号：US08711652B2
公开(公告)日：2014-04-29
申请号：US12658911
申请日：2010-02-17
申请人： Young-Min Lee , Sung-Jae Byun , Han-Gu Sohn , Gyoo-Cheol Hwang
发明人： Young-Min Lee , Sung-Jae Byun , Han-Gu Sohn , Gyoo-Cheol Hwang
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C7/1075 , G11C11/406 , G11C11/40603 , G11C11/40611
摘要： A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS and PALL commands, for prevention of collision of commands, refresh starvation, and/or a missing pre-charge operation in the shared memory device.
摘要翻译：多个主机在使用软件和仲裁接口之间仲裁以访问诸如SDRAM（同步动态随机存取存储器）之类的共享存储器设备。主机在仲裁时产生附加命令，例如MRS和PALL命令，用于防止命令冲突，刷新饥饿和/或在共享存储器设备中缺少预充电操作。

8. 发明授权

US07697362B2 Arbitration for memory device with commands 有权
标题翻译：带指令的内存设备仲裁
公开(公告)号：US07697362B2
公开(公告)日：2010-04-13
申请号：US11521655
申请日：2006-09-15
申请人： Young-Min Lee , Sung-Jae Byun , Han-Gu Sohn , Gyoo-Cheol Hwang
发明人： Young-Min Lee , Sung-Jae Byun , Han-Gu Sohn , Gyoo-Cheol Hwang
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C7/1075 , G11C11/406 , G11C11/40603 , G11C11/40611
摘要： A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS and PALL commands, for prevention of collision of commands, refresh starvation, and/or a missing pre-charge operation in the shared memory device.
摘要翻译：多个主机在使用软件和仲裁接口之间仲裁以访问诸如SDRAM（同步动态随机存取存储器）之类的共享存储器设备。主机在仲裁时产生附加命令，例如MRS和PALL命令，用于防止命令冲突，刷新饥饿和/或在共享存储器设备中缺少预充电操作。

9. 发明申请

US20090210691A1 Memory System and Memory Management Method Including the Same 有权
标题翻译：内存系统和内存管理方法包括它
公开(公告)号：US20090210691A1
公开(公告)日：2009-08-20
申请号：US12430722
申请日：2009-04-27
申请人： Jeon-Taek Im , Young-Min Lee , Han-Gu Sohn , Jin-Hyoung Kwon , Sung-Jae Byun , Yun-Tae Lee , Gyoo-Cheol Hwang
发明人： Jeon-Taek Im , Young-Min Lee , Han-Gu Sohn , Jin-Hyoung Kwon , Sung-Jae Byun , Yun-Tae Lee , Gyoo-Cheol Hwang
IPC分类号： G06F15/177
CPC分类号： G06F12/0607 , G06F9/4405 , G06F9/445 , G06F12/0638 , G06F15/177 , G06F2212/2022 , G11C8/16
摘要： A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.
摘要翻译：提供了具有第一处理器和第二处理器的数字处理的启动方法。第一处理器和外部之间的接口被停止。第二处理器程序代码从第一存储器发送到第二存储器。用于第一处理器的第二级装载器（SSL）从第一存储器发送到第二处理器的缓冲器。第一处理器程序代码在第二处理器的控制下从第一存储器发送到第二存储器，并且恢复第一处理器和外部之间的接口。第一处理器程序代码被快速下载到第二个存储器中以减少数字处理系统的引导时间。

10. 发明授权

US07791964B2 Memory system and method ensuring read data stability 失效
标题翻译：内存系统和方法确保读取数据的稳定性
公开(公告)号：US07791964B2
公开(公告)日：2010-09-07
申请号：US12044174
申请日：2008-03-07
申请人： Young-Min Lee , Han-Gu Sohn
发明人： Young-Min Lee , Han-Gu Sohn
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： A memory system and related method of operation are disclosed. The memory system includes a memory configured to generate a data strobe signal including “(n/2)+1” clock signals, where “n” is a number of base data blocks in read data synchronously transferred by the memory during a read operation, and a memory controller configured to receive the read data, receive the data strobe signal, delay the data strobe signal to generate a delayed data strobe signal, and synchronously output “n/2” sampled data blocks to a requesting device in relation to the delayed data strobe signal.
摘要翻译：公开了一种存储系统及其相关操作方法。存储器系统包括被配置为产生包括“（n / 2）+1”个时钟信号的数据选通信号的存储器，其中“n”是在读取操作期间由存储器同步传送的读取数据中的基本数据块的数量，以及存储器控制器，被配置为接收所读取的数据，接收数据选通信号，延迟数据选通信号以产生延迟的数据选通信号，并且相对于所延迟的数据选通信号同步地将“n / 2”个采样数据块输出到请求设备数据选通信号。

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