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1. 发明授权

US09275598B2 DAC architecture for LCD source driver 有权
标题翻译： DAC架构用于LCD源驱动
公开(公告)号：US09275598B2
公开(公告)日：2016-03-01
申请号：US12859888
申请日：2010-08-20
申请人： Nang-Ping Tu , Fu-Lung Hsueh , Mingo Liu
发明人： Nang-Ping Tu , Fu-Lung Hsueh , Mingo Liu
IPC分类号： G09G3/36 , H03M1/68 , H03M1/72 , H03M1/76 , H03M1/80
CPC分类号： G09G3/3696 , G09G3/3688 , G09G2310/027 , H03M1/687 , H03M1/72 , H03M1/76 , H03M1/804 , H03M1/806
摘要： A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.
摘要翻译：用于响应于M位数字输入代码输出模拟电压的两级数模转换器包括具有高参考电压输入节点的两位串行电荷再分配数模转换器，用于接收高电平参考电压和用于接收低参考电压的低参考电压输入节点，以及电压选择器。电压选择器将高参考电压和低参考电压设置为所选电平，这取决于至少一部分M位数字输入代码。

2. 发明授权

US08981979B2 Integrated circuits, liquid crystal display (LCD) drivers, and systems 有权
标题翻译：集成电路，液晶显示（LCD）驱动器和系统
公开(公告)号：US08981979B2
公开(公告)日：2015-03-17
申请号：US13466608
申请日：2012-05-08
申请人： Nang-Ping Tu , Fu-Lung Hsueh , Mingo Liu , I-Fey Wang
发明人： Nang-Ping Tu , Fu-Lung Hsueh , Mingo Liu , I-Fey Wang
IPC分类号： H03M1/66 , G09G3/36 , H03M1/76
CPC分类号： H03M1/66 , G09G3/3648 , G09G3/3685 , G09G2310/027 , G09G2310/0286 , G09G2310/0289 , G09G2310/0294 , H03M1/662 , H03M1/765
摘要： An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.
摘要翻译：集成电路包括数模转换器（DAC）电路，其包括至少一个第一通道类型DAC和至少一个第二通道类型DAC。集成电路包括多个采样和保持（S / H）电路。每个S / H电路与DAC电路耦合。 S / H电路能够从DAC电路接收信号并并行输出信号。

3. 发明申请

US20110261084A1 DAC ARCHITECTURE FOR LCD SOURCE DRIVER 有权
标题翻译：用于LCD源驱动器的DAC架构
公开(公告)号：US20110261084A1
公开(公告)日：2011-10-27
申请号：US12859888
申请日：2010-08-20
申请人： Nang-Ping TU , Fu-Lung HSUEH , Mingo LIU
发明人： Nang-Ping TU , Fu-Lung HSUEH , Mingo LIU
IPC分类号： G09G3/36 , H03M1/06 , G09G5/10 , H03M1/66
CPC分类号： G09G3/3696 , G09G3/3688 , G09G2310/027 , H03M1/687 , H03M1/72 , H03M1/76 , H03M1/804 , H03M1/806
摘要： A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.
摘要翻译：用于响应于M位数字输入代码输出模拟电压的两级数模转换器包括具有高参考电压输入节点的两位串行电荷再分配数模转换器，用于接收高电平参考电压和用于接收低参考电压的低参考电压输入节点，以及电压选择器。电压选择器将高参考电压和低参考电压设置为所选电平，这取决于至少一部分M位数字输入代码。

4. 发明申请

US20140001518A1 Integrated Circuit Devices with Well Regions and Methods for Forming the Same 审中-公开
标题翻译：具有井区的集成电路器件及其形成方法
公开(公告)号：US20140001518A1
公开(公告)日：2014-01-02
申请号：US13539027
申请日：2012-06-29
申请人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Mingo Liu
发明人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Mingo Liu
IPC分类号： H01L27/07 , H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/07 , H01L27/085 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/732 , H01L29/7327 , H01L29/808 , H01L29/861 , H01L29/93
摘要： A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.
摘要翻译：一种方法包括在衬底中形成第一导电类型的深阱区域，注入深阱区域的一部分以形成第一栅极，以及植入深阱区域以形成阱区域。阱区和第一栅极是与第一导电类型相反的第二导电类型。执行注入以在第一栅极上形成第一导电类型的沟道区。植入覆盖沟道区域的深阱区域的一部分以形成第二导电类型的第二栅极。进行源极/漏极注入以在第二栅极的相对侧上形成第一导电类型的源极区域和漏极区域。源极和漏极区域连接到沟道区域，并且与沟道区域和第一栅极重叠。

5. 发明申请

US20120025389A1 Hermetic Wafer Level Packaging 有权
标题翻译：密封晶圆级包装
公开(公告)号：US20120025389A1
公开(公告)日：2012-02-02
申请号：US12846504
申请日：2010-07-29
申请人： Richard Chu , Martin Liu , Chia-Hua Chu , Yuan-Chih Hsieh , Chung-Hsien Lin , Lan-Lin Chao , Chun-Wen Cheng , Mingo Liu
发明人： Richard Chu , Martin Liu , Chia-Hua Chu , Yuan-Chih Hsieh , Chung-Hsien Lin , Lan-Lin Chao , Chun-Wen Cheng , Mingo Liu
IPC分类号： H01L23/52 , H01L21/50
CPC分类号： H01L24/94 , B81B2207/015 , B81C1/00269 , B81C2203/0109 , B81C2203/0771 , H01L23/481 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/1306 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.
摘要翻译：提供晶圆级封装。该封装包括具有晶体管器件的第一半导体晶片和包括第一材料的第一结合层。所述封装包括具有第二接合层的第二半导体晶片，所述第二接合层包括不同于所述第一材料的第二材料，所述第一和第二材料中的一个为铝基，另一个为钛基。其中第二晶片的一部分通过第一和第二接合层扩散地结合到第一晶片。

6. 发明授权

US08012785B2 Method of fabricating an integrated CMOS-MEMS device 有权
标题翻译：制造集成CMOS-MEMS器件的方法
公开(公告)号：US08012785B2
公开(公告)日：2011-09-06
申请号：US12429305
申请日：2009-04-24
申请人： Kai-Chih Liang , Hua-Shu Wu , Li-Chun Peng , Tsung-Cheng Huang , Mingo Liu , Nick Y. M. Shen , Allen Timothy Chang
发明人： Kai-Chih Liang , Hua-Shu Wu , Li-Chun Peng , Tsung-Cheng Huang , Mingo Liu , Nick Y. M. Shen , Allen Timothy Chang
IPC分类号： H01L21/00 , H01L27/14
CPC分类号： B81C1/00246 , B81B2201/0257 , B81C2201/056 , B81C2203/0714 , B81C2203/0728
摘要： An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside of the substrate. The MEMS mechanical structure is then released. A protective layer is formed on the frontside of the substrate. The protective layer is disposed on the released MEMS mechanical structure (e.g., protects the MEMS structure). The backside of the substrate is processed while the protective layer is disposed on the MEMS mechanical structure.
摘要翻译：提供了一种方法的实施例，其包括提供具有前侧和后侧的基底。在衬底上形成CMOS器件。在该基板上也形成有MEMS器件。形成MEMS器件包括在衬底的前侧形成MEMS机械结构。然后释放MEMS机械结构。在基板的前侧形成有保护层。保护层设置在释放的MEMS机械结构上（例如，保护MEMS结构）。在保护层设置在MEMS机械结构上的同时处理衬底的背面。

7. 发明授权

US06797528B2 Micro probing tip made by micro machine method 失效
标题翻译：微型探针微探针法制成
公开(公告)号：US06797528B2
公开(公告)日：2004-09-28
申请号：US10053224
申请日：2002-01-17
申请人： Mingo Liu , Jeng-Han Lee
发明人： Mingo Liu , Jeng-Han Lee
IPC分类号： G01R3126
CPC分类号： G01R3/00
摘要： A method and apparatus for forming a micro tip for a micro probe utilized in testing semiconductor integrated circuit devices. A thick oxide layer is deposited upon a substrate initially to form the micro tip. The micro tip for the micro probe can be defined from the thick oxide layer upon the substrate through a plurality of subsequent semiconductor manufacturing operations performed upon the substrate and layers thereof. A plurality of micro tips can be mass produced and efficiently utilized in association with increasingly smaller sizes of semiconductor integrated circuit devices.
摘要翻译：一种用于形成用于测试半导体集成电路器件的微探头微尖的方法和装置。最初将厚氧化层沉积在基底上以形成微尖端。用于微探针的微尖端可以通过在衬底及其层上执行的多个随后的半导体制造操作从衬底上的厚氧化物层定义。可以与越来越小尺寸的半导体集成电路器件相关联地大量生产和有效地利用多个微尖端。

8. 发明授权

US10269658B2 Integrated circuit devices with well regions and methods for forming the same 有权
公开(公告)号：US10269658B2
公开(公告)日：2019-04-23
申请号：US13539027
申请日：2012-06-29
申请人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Mingo Liu
发明人： Chi-Feng Huang , Chia-Chung Chen , Victor Chiang Liang , Mingo Liu
IPC分类号： H01L27/07 , H01L21/8249 , H01L27/06 , H01L27/085 , H01L29/732 , H01L29/808 , H01L29/861 , H01L29/93 , H01L29/06
摘要： A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

9. 发明授权

US08648468B2 Hermetic wafer level packaging 有权
标题翻译：密封晶圆级包装
公开(公告)号：US08648468B2
公开(公告)日：2014-02-11
申请号：US12846504
申请日：2010-07-29
申请人： Richard Chu , Martin Liu , Chia-Hua Chu , Yuan-Chih Hsieh , Chung-Hsien Lin , Lan-Lin Chao , Chun-Wen Cheng , Mingo Liu
发明人： Richard Chu , Martin Liu , Chia-Hua Chu , Yuan-Chih Hsieh , Chung-Hsien Lin , Lan-Lin Chao , Chun-Wen Cheng , Mingo Liu
IPC分类号： H01L23/48
CPC分类号： H01L24/94 , B81B2207/015 , B81C1/00269 , B81C2203/0109 , B81C2203/0771 , H01L23/481 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/1306 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum -based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.
摘要翻译：提供晶圆级封装。该封装包括具有晶体管器件的第一半导体晶片和包括第一材料的第一结合层。所述封装包括具有第二接合层的第二半导体晶片，所述第二接合层包括不同于所述第一材料的第二材料，所述第一和第二材料中的一个为铝基，另一个为钛基。其中第二晶片的一部分通过第一和第二接合层扩散地结合到第一晶片。

10. 发明授权

US08338906B2 Schottky device 有权
标题翻译：肖特基装置
公开(公告)号：US08338906B2
公开(公告)日：2012-12-25
申请号：US12329677
申请日：2008-12-08
申请人： Ping-Chun Yeh , Der-Chyang Yeh , Ruey-Hsin Liu , Mingo Liu
发明人： Ping-Chun Yeh , Der-Chyang Yeh , Ruey-Hsin Liu , Mingo Liu
IPC分类号： H01L29/66
CPC分类号： H01L27/0814 , H01L29/0692 , H01L29/417 , H01L29/872
摘要： An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region. A conductive contact is in contact with the internal portion and the outer portion of the metal silicide layer.
摘要翻译：集成电路结构具有形成在n型阱区上的金属硅化物层，形成在n型阱区上并环绕金属硅化物层的p型保护环。金属硅化物层的外部部分延伸成与保护环的内边缘重叠，并且在金属硅化物层的内部部分与阱区域的接合处形成肖特基势垒。导电接触件与金属硅化物层的内部部分和外部部分接触。

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