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1. 发明授权

US10152450B2 Remote processing and memory utilization 有权
公开(公告)号：US10152450B2
公开(公告)日：2018-12-11
申请号：US13584323
申请日：2012-08-13
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F15/167 , G06F15/173 , G06F9/54 , H04L29/06 , H04L29/08
摘要： According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.

2. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

3. 发明授权

US09077616B2 T-star interconnection network topology 有权
标题翻译： T星互连网络拓扑
公开(公告)号：US09077616B2
公开(公告)日：2015-07-07
申请号：US13569789
申请日：2012-08-08
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
IPC分类号： H04L12/24 , H04L12/715
CPC分类号： H04L41/0663 , H04L41/12 , H04L41/145 , H04L45/04
摘要： According to one embodiment of the present invention, a system for network communication includes an M dimensional grid of node groups, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one and each node comprises a router and intra-group links directly connecting each node in each node group to every other node in the node group. In addition, the system includes inter-group links directly connecting each node in each node group to a node in each neighboring node group in the M dimensional grid.
摘要翻译：根据本发明的一个实施例，一种用于网络通信的系统包括节点组的M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N大于1，并且每个节点包括路由器和组内链路，将每个节点组中的每个节点直接连接到节点组中的每个其他节点。此外，该系统包括将每个节点组中的每个节点直接连接到M维网格中的每个相邻节点组中的节点的组间链路。

4. 发明授权

US08924763B2 Synchronizing compute node time bases in a parallel computer 有权
标题翻译：在并行计算机中同步计算节点时基
公开(公告)号：US08924763B2
公开(公告)日：2014-12-30
申请号：US13327107
申请日：2011-12-15
申请人： Dong Chen , Daniel A. Faraj , Thomas M. Gooding , Philip Heidelberger
发明人： Dong Chen , Daniel A. Faraj , Thomas M. Gooding , Philip Heidelberger
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , H04L12/413
摘要： Synchronizing time bases in a parallel computer that includes compute nodes organized for data communications in a tree network, where one compute node is designated as a root, and, for each compute node: calculating data transmission latency from the root to the compute node; configuring a thread as a pulse waiter; initializing a wakeup unit; and performing a local barrier operation; upon each node completing the local barrier operation, entering, by all compute nodes, a global barrier operation; upon all nodes entering the global barrier operation, sending, to all the compute nodes, a pulse signal; and for each compute node upon receiving the pulse signal: waking, by the wakeup unit, the pulse waiter; setting a time base for the compute node equal to the data transmission latency between the root node and the compute node; and exiting the global barrier operation.
摘要翻译：在并行计算机中同步时基，其包括为树网络中的数据通信而组织的计算节点，其中一个计算节点被指定为根，并且对于每个计算节点，计算从根到计算节点的数据传输等待时间; 将线程配置为脉冲服务员; 初始化唤醒单元; 并执行局部屏障操作; 在每个节点完成局部屏障操作时，由所有计算节点进入全局屏障操作; 在所有节点进入全局屏障操作之后，向所有计算节点发送脉冲信号; 并且对于每个计算节点在接收到脉冲信号时：由唤醒单元唤醒脉冲服务员; 为计算节点设置等于根节点和计算节点之间的数据传输延迟的时基; 并退出全球屏障操作。

5. 发明授权

US08856490B2 Optimizing TLB entries for mixed page size storage in contiguous memory 有权
标题翻译：优化连续内存中混合页大小存储的TLB条目
公开(公告)号：US08856490B2
公开(公告)日：2014-10-07
申请号：US13618730
申请日：2012-09-14
申请人： Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Jon K. Kriegel , Martin Ohmacht , Burkhard Steinmacher-Burow
发明人： Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Jon K. Kriegel , Martin Ohmacht , Burkhard Steinmacher-Burow
IPC分类号： G06F12/06 , G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652 , G06F2212/654
摘要： A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.
摘要翻译：提供了一种访问存储器的系统和方法。该系统包括用于存储一个或多个页表条目的查找缓冲器，其中所述一个或多个页表条目中的每一个包括至少虚拟页码和物理页号; 用于从所述处理器接收虚拟地址的逻辑电路，所述逻辑电路用于将所述虚拟地址与所述页表项之一中的虚拟页号进行匹配，以选择所述同一页表项中的所述物理页号，所述页表项具有一个或多个位被设置为从页面排除存储器范围。

6. 发明授权

US08756350B2 Method and apparatus for efficiently tracking queue entries relative to a timestamp 失效
标题翻译：相对于时间戳有效跟踪队列条目的方法和装置
公开(公告)号：US08756350B2
公开(公告)日：2014-06-17
申请号：US11768800
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F12/0835 , G06F12/0831
摘要： An apparatus and method for tracking coherence event signals transmitted in a multiprocessor system. The apparatus comprises a coherence logic unit, each unit having a plurality of queue structures with each queue structure associated with a respective sender of event signals transmitted in the system. A timing circuit associated with a queue structure controls enqueuing and dequeuing of received coherence event signals, and, a counter tracks a number of coherence event signals remaining enqueued in the queue structure and dequeued since receipt of a timestamp signal. A counter mechanism generates an output signal indicating that all of the coherence event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. In one embodiment, the timestamp signal is asserted at the start of a memory synchronization operation and, the output signal indicates that all coherence events present when the timestamp signal was asserted have completed. This signal can then be used as part of the completion condition for the memory synchronization operation.
摘要翻译：一种用于跟踪在多处理器系统中发送的相干事件信号的装置和方法。该装置包括相干逻辑单元，每个单元具有多个队列结构，每个队列结构与在系统中传输的事件信号的相应发送者相关联。与队列结构相关联的定时电路控制接收的相干事件信号的排队和出队，并且计数器跟踪队列结构中剩余入队的多个相干事件信号，并且从接收到时间戳信号起出队。计数器机构产生一个输出信号，指示在接收时间戳信号时存在于队列结构中的所有相干事件信号已经出队。在一个实施例中，时间戳信号在存储器同步操作的开始被断言，并且输出信号指示当时间戳信号被断言时存在的所有相干事件已经完成。然后可以将该信号用作存储器同步操作的完成条件的一部分。

7. 发明申请

US20140044006A1 T-STAR INTERCONNECTION NETWORK TOPOLOGY 有权
标题翻译： T-STAR互联网络拓扑
公开(公告)号：US20140044006A1
公开(公告)日：2014-02-13
申请号：US13569789
申请日：2012-08-08
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
IPC分类号： H04L12/28
CPC分类号： H04L41/0663 , H04L41/12 , H04L41/145 , H04L45/04
摘要： According to one embodiment of the present invention, a system for network communication includes an M dimensional grid of node groups, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one and each node comprises a router and intra-group links directly connecting each node in each node group to every other node in the node group. In addition, the system includes inter-group links directly connecting each node in each node group to a node in each neighboring node group in the M dimensional grid.
摘要翻译：根据本发明的一个实施例，一种用于网络通信的系统包括节点组的M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N大于1，并且每个节点包括路由器和组内链路，将每个节点组中的每个节点直接连接到节点组中的每个其他节点。此外，该系统包括将每个节点组中的每个节点直接连接到M维网格中的每个相邻节点组中的节点的组间链路。

8. 发明授权

US08521990B2 Embedding global barrier and collective in torus network with each node combining input from receivers according to class map for output to senders 有权
标题翻译：在环网中嵌入全局屏障和集体，每个节点根据类映射将接收器的输入组合到输出到发送器
公开(公告)号：US08521990B2
公开(公告)日：2013-08-27
申请号：US12723277
申请日：2010-03-12
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Philip Heidelberger , Robert M. Senger , Valentina Salapura , Burkhard Steinmacher-Burow , Yutaka Sugawara , Todd E. Takken
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Philip Heidelberger , Robert M. Senger , Valentina Salapura , Burkhard Steinmacher-Burow , Yutaka Sugawara , Todd E. Takken
IPC分类号： G06F15/16
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
摘要翻译：本发明的实施例提供了一种用于在被组织为环面网络的并行计算机系统中嵌入全局屏障和全局中断网络的方法，系统和计算机程序产品。计算机系统包括多个节点。在一个实施例中，该方法包括从节点的一组接收器中获取输入，将来自接收器的输入划分为多个类，组合每个类的输入以获得结果，并将所述结果发送到一组的节点的发送者。本发明的实施例提供了一种用于将集体网络嵌入组织为环面网络的并行计算机系统中的方法，系统和计算机程序产品。在一个实施例中，该方法包括向环形网络添加集中逻辑以在树结构中的至少一组节点之间路由消息。

9. 发明申请

US20130159760A1 Synchronizing Compute Node Time Bases In A Parallel Computer 有权
标题翻译：在并行计算机中同步计算节点时基
公开(公告)号：US20130159760A1
公开(公告)日：2013-06-20
申请号：US13327107
申请日：2011-12-15
申请人： Dong Chen , Daniel A. Faraj , Thomas M. Gooding , Philip Heidelberger
发明人： Dong Chen , Daniel A. Faraj , Thomas M. Gooding , Philip Heidelberger
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , H04L12/413
摘要： Synchronizing time bases in a parallel computer that includes compute nodes organized for data communications in a tree network, where one compute node is designated as a root, and, for each compute node: calculating data transmission latency from the root to the compute node; configuring a thread as a pulse waiter; initializing a wakeup unit; and performing a local barrier operation; upon each node completing the local barrier operation, entering, by all compute nodes, a global barrier operation; upon all nodes entering the global barrier operation, sending, to all the compute nodes, a pulse signal; and for each compute node upon receiving the pulse signal: waking, by the wakeup unit, the pulse waiter; setting a time base for the compute node equal to the data transmission latency between the root node and the compute node; and exiting the global barrier operation.
摘要翻译：在并行计算机中同步时基，其包括为树网络中的数据通信而组织的计算节点，其中一个计算节点被指定为根，并且对于每个计算节点，计算从根到计算节点的数据传输等待时间; 将线程配置为脉冲服务员; 初始化唤醒单元; 并执行局部屏障操作; 在每个节点完成局部屏障操作时，由所有计算节点进入全局屏障操作; 在所有节点进入全局屏障操作之后，向所有计算节点发送脉冲信号; 并且对于每个计算节点在接收到脉冲信号时：由唤醒单元唤醒脉冲服务员; 为计算节点设置等于根节点和计算节点之间的数据传输延迟的时基; 并退出全球屏障操作。

10. 发明授权

US08468416B2 Combined group ECC protection and subgroup parity protection 有权
标题翻译：组合组ECC保护和子组奇偶校验保护
公开(公告)号：US08468416B2
公开(公告)日：2013-06-18
申请号：US11768527
申请日：2007-06-26
申请人： Alan G. Gara , Dong Chen , Philip Heidelberger , Martin Ohmacht
发明人： Alan G. Gara , Dong Chen , Philip Heidelberger , Martin Ohmacht
IPC分类号： H03M13/00
CPC分类号： G06F11/1076 , G06F11/1064 , G06F2212/403 , H03M1/0687 , H03M13/13 , H03M13/2707 , H03M13/271 , H03M13/29 , H03M13/616
摘要： A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.
摘要翻译：公开了用于为给定的n位组提供组合的错误代码保护和子组奇偶校验保护的方法和系统。该方法包括以下步骤：识别用于所述错误保护的冗余位的数量m; 并且构造矩阵P，其中将所述给定的n个比特组与P相乘产生m个冗余纠错码（ECC）保护比特，并且两列P为所述给定组n比特的子组提供奇偶校验保护。在本发明的优选实施例中，矩阵P是通过产生具有三个或更多个奇数个元素的m位宽向量的排列而构成的，其中值为1的元素和其他元素的值为零; 并将所述向量分配给矩阵P的行。

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