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1. 发明授权

US09805340B2 Methods and apparatus for managing and distinguishing instant messaging sessions and threads 有权
公开(公告)号：US09805340B2
公开(公告)日：2017-10-31
申请号：US12056737
申请日：2008-03-27
申请人： Jarir Kamel Chaar , Neal Martin Keller , Clifford Alan Pickover , Robert W. Wisniewski
发明人： Jarir Kamel Chaar , Neal Martin Keller , Clifford Alan Pickover , Robert W. Wisniewski
IPC分类号： G06F15/16 , G06Q10/10 , G06F3/0482 , H04L12/58
CPC分类号： G06Q10/107 , G06F3/0482 , H04L51/04
摘要： A method of managing instant messaging communication over a computer network is provided. One or more instant messaging session windows are organized in an instant messaging session manager. At least one distinguishing session characteristic is attributed to each of the one or more instant messaging session windows. The at least one distinguishing session characteristic is at least one of a sound clip associated with a user of the session, an instant messaging session window background associated with a user of the session, and a change in at least one of a color and an intensity of the instant messaging session window. The at least one distinguishing session characteristic increases a likelihood of identification of each of the one or more instant messaging session windows.

2. 发明授权

US09195550B2 Method for guaranteeing program correctness using fine-grained hardware speculative execution 有权
标题翻译：使用细粒度硬件推测执行来保证程序正确性的方法
公开(公告)号：US09195550B2
公开(公告)日：2015-11-24
申请号：US13020228
申请日：2011-02-03
申请人： Dan Tsafrir , Robert W. Wisniewski
发明人： Dan Tsafrir , Robert W. Wisniewski
IPC分类号： G06F11/08 , G06F11/14 , G06F9/38 , G06F12/08 , G06F9/46 , G06F9/52
CPC分类号： G06F11/1489 , G06F9/3851 , G06F9/466 , G06F9/467 , G06F9/528 , G06F12/0842 , G06F12/0846
摘要： A method for checking program correctness may include executing a program on a main hardware thread in speculative execution mode on a hardware execution context on a chip having a plurality of hardware execution contexts. In this mode, the main hardware thread's state is not committed to main memory. Correctness checks by a plurality of helper threads are executed in parallel to the main hardware thread. Each helper thread runs on a separate hardware execution context on the chip in parallel with the main hardware thread. The correctness checks determine a safe point in the program up to which the operations executed by the main hardware thread are correct. Once the main hardware thread reaches the safe point, the mode of execution of the main hardware thread is switched to non-speculative. The runtime then causes the main thread to re-enter speculative mode of execution.
摘要翻译：用于检查程序正确性的方法可以包括在具有多个硬件执行上下文的芯片上的硬件执行上下文上以推测执行模式在主硬件线程上执行程序。在这种模式下，主硬件线程的状态不会被提供给主内存。多个辅助线程的正确性检查与主硬件线程并行执行。每个辅助线程与主要硬件线程并行运行在芯片上的单独硬件执行环境上。正确性检查确定程序中的安全点，主要硬件线程执行的操作是正确的。一旦主要硬件线程到达安全点，主硬件线程的执行模式切换为非投机模式。然后运行时使主线程重新输入推测的执行模式。

3. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

4. 发明授权

US08918799B2 Method to utilize cores in different operating system partitions 有权
标题翻译：在不同操作系统分区中使用内核的方法
公开(公告)号：US08918799B2
公开(公告)日：2014-12-23
申请号：US13435100
申请日：2012-03-30
申请人： Todd A. Inglett , Yoonho Park , Bryan S. Rosenburg , Robert W. Wisniewski
发明人： Todd A. Inglett , Yoonho Park , Bryan S. Rosenburg , Robert W. Wisniewski
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： G06F9/545 , G06F9/5077 , Y02D10/22 , Y02D10/36
摘要： A system call utility may be provided on a first operating system managing a first hardware computing entity. The system call utility may take as an argument a pointer to a computer code a second operating system established to run on the first hardware computing entity. The first operating system is enabled to execute the computer code natively on the first hardware computing entity, and return a result of the computer code executed on the first hardware computing entity to the second operating system.
摘要翻译：可以在管理第一硬件计算实体的第一操作系统上提供系统调用实用程序。系统调用实用程序可以将建立为在第一硬件计算实体上运行的第二操作系统的指针作为计算机代码的指针。第一操作系统能够在第一硬件计算实体上本地执行计算机代码，并将在第一硬件计算实体上执行的计算机代码的结果返回给第二操作系统。

5. 发明授权

US08621167B2 Using DMA for copying performance counter data to memory 失效
标题翻译：使用DMA将性能计数器数据复制到存储器
公开(公告)号：US08621167B2
公开(公告)日：2013-12-31
申请号：US13446467
申请日：2012-04-13
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F13/28 , G06F11/34 , G06F2201/88
摘要： A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.
摘要翻译：用于复制性能计数器数据的设备包括将直接存储器访问（DMA）单元连接到多个硬件性能计数器和存储器设备的硬件路径。软件为DMA单元准备一个注入数据包来执行复制，而软件可以执行其他任务。在一个方面，准备注射分组的软件在收集硬件性能计数器数据的核心以外的处理核上运行。

6. 发明申请

US20130326180A1 MECHANISM FOR OPTIMIZED INTRA-DIE INTER-NODELET MESSAGING COMMUNICATION 有权
标题翻译：优化内部信号通信通信机制
公开(公告)号：US20130326180A1
公开(公告)日：2013-12-05
申请号：US13485074
申请日：2012-05-31
申请人： Amith R. Mamidala , Valentina Salapura , Robert W. Wisniewski
发明人： Amith R. Mamidala , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/14
CPC分类号： G06F9/544 , G06F15/167
摘要： Point-to-point intra-nodelet messaging support for nodelets on a single chip that obey MPI semantics may be provided. In one aspect, a local buffering mechanism is employed that obeys standard communication protocols for the network communications between the nodelets integrated in a single chip. Sending messages from one nodelet to another nodelet on the same chip may be performed not via the network, but by exchanging messages in the point-to-point messaging buckets between the nodelets. The messaging buckets need not be part of the memory system of the nodelets. Specialized hardware controllers may be used for moving data between the nodelets and each messaging bucket, and ensuring correct operation of the network protocol.
摘要翻译：可以提供在遵循MPI语义的单个芯片上的节点的点对点节点内消息支持。在一个方面，采用本地缓冲机制，其遵循集成在单个芯片中的节点之间的网络通信的标准通信协议。从同一芯片上的一个节点发送消息到另一个节点可能不是通过网络执行的，而是通过在节点之间的点对点消息存储区中交换消息。消息传递桶不需要是节点的内存系统的一部分。专用硬件控制器可用于在节点和每个消息传送桶之间移动数据，并确保网络协议的正确操作。

7. 发明申请

US20120204065A1 METHOD FOR GUARANTEEING PROGRAM CORRECTNESS USING FINE-GRAINED HARDWARE SPECULATIVE EXECUTION 有权
标题翻译：使用细粒度分布式执行程序保证程序正确性的方法
公开(公告)号：US20120204065A1
公开(公告)日：2012-08-09
申请号：US13020228
申请日：2011-02-03
申请人： Dan Tsafrir , Robert W. Wisniewski
发明人： Dan Tsafrir , Robert W. Wisniewski
IPC分类号： G06F11/36
CPC分类号： G06F11/1489 , G06F9/3851 , G06F9/466 , G06F9/467 , G06F9/528 , G06F12/0842 , G06F12/0846
摘要： A method for checking program correctness may include executing a program on a main hardware thread in speculative execution mode on a hardware execution context on a chip having a plurality of hardware execution contexts. In this mode, the main hardware thread's state is not committed to main memory. Correctness checks by a plurality of helper threads are executed in parallel to the main hardware thread. Each helper thread runs on a separate hardware execution context on the chip in parallel with the main hardware thread. The correctness checks determine a safe point in the program up to which the operations executed by said main hardware thread are correct. Once the main hardware thread reaches the safe point, the mode of execution of the main hardware thread is switched to non-speculative. The runtime then causes the main thread to re-enter speculative mode of execution.
摘要翻译：用于检查程序正确性的方法可以包括在具有多个硬件执行上下文的芯片上的硬件执行上下文上以推测执行模式在主硬件线程上执行程序。在这种模式下，主硬件线程的状态不会被提供给主内存。多个辅助线程的正确性检查与主硬件线程并行执行。每个辅助线程与主要硬件线程并行运行在芯片上的单独硬件执行环境上。正确性检查确定程序中的安全点，所述主要硬件线程执行的操作是正确的。一旦主要硬件线程到达安全点，主硬件线程的执行模式切换为非投机模式。然后运行时使主线程重新输入推测的执行模式。

8. 发明申请

US20120179896A1 METHOD AND APPARATUS FOR A HIERARCHICAL SYNCHRONIZATION BARRIER IN A MULTI-NODE SYSTEM 审中-公开
标题翻译：多节点系统中分层同步障碍的方法与装置
公开(公告)号：US20120179896A1
公开(公告)日：2012-07-12
申请号：US12987523
申请日：2011-01-10
申请人： Valentina Salapura , Robert W. Wisniewski
发明人： Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F9/30
CPC分类号： G06F9/522 , G06F9/30087 , G06F9/3851
摘要： A hierarchical barrier synchronization of cores and nodes on a multiprocessor system, in one aspect, may include providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier; determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals; determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed; in response to determining that all of the plurality of threads on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed.
摘要翻译：在一个方面，多处理器系统上的核心和节点的层级屏障同步可以包括：响应于达到屏障，将芯片上的多个线程中的每一个提供给寄存器中的相应位的输入比特信号; 确定所有多个线程是否通过将所述寄存器的位电一体化并将所述输入位信号“AND”到达所述障碍物; 确定是否仅需要片上同步或者是否需要节点间同步; 响应于确定芯片上的所有多个线程到达屏障，通知芯片上的多个线程，如果确定仅需要片上同步; 并且如果确定需要节点间同步，则在芯片上的所有多个线程到达屏障之后，将同步信号传送到芯片外部。

9. 发明授权

US08140764B2 System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory 有权
标题翻译：用于重新配置具有与下级高速缓冲存储器的扇区相关联的访问位的高速缓冲存储器的系统和与上级高速缓冲存储器的扇区相关联的粒度位
公开(公告)号：US08140764B2
公开(公告)日：2012-03-20
申请号：US12985726
申请日：2011-01-06
申请人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
发明人： Xiaowei Shen , Balaram Sinharoy , Robert B. Tremaine , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.
摘要翻译：提供了一种重新配置高速缓冲存储器的方法。一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。

10. 发明申请

US20110173588A1 HARDWARE SUPPORT FOR SOFTWARE CONTROLLED FAST MULTIPLEXING OF PERFORMANCE COUNTERS 失效
标题翻译：软件支持软件控制性能计数器的快速多路复用
公开(公告)号：US20110173588A1
公开(公告)日：2011-07-14
申请号：US12684429
申请日：2010-01-08
申请人： Valentina Salapura , Robert W. Wisniewski
发明人： Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F9/44
CPC分类号： G06F11/348 , G06F2201/88
摘要： Hardware support for software controlled fast multiplexing of performance counters may include a plurality of performance counters operable to collect one or more counts of one or more selected activities, and a plurality of registers operable to store a set of performance counter configurations. A state machine may be operable to automatically select a register from the plurality of registers for reconfiguring the one or more performance counters in response to receiving a first signal. The state machine may be further operable to reconfigure the one or more performance counters based on a configuration specified in the selected register. The state machine yet further may be operable to copy data in selected one or more of the plurality of performance counters to a memory location, or to copy data from the memory location to the counters, in response to receiving a second signal. The state machine may be operable to store or restore the counter values and state machine configuration in response to a context switch event.
摘要翻译：用于性能计数器的软件控制快速复用的硬件支持可以包括可操作以收集一个或多个所选活动的一个或多个计数的多个性能计数器，以及可操作以存储一组性能计数器配置的多个寄存器。状态机可操作以响应于接收第一信号而自动地从多个寄存器中选择一个寄存器来重新配置一个或多个性能计数器。状态机可以进一步可操作以基于所选择的寄存器中指定的配置重新配置一个或多个性能计数器。状态机还可以用于响应于接收第二信号，将多个性能计数器中选定的一个或多个性能计数器中的数据复制到存储器位置，或者将数据从存储器位置复制到计数器。状态机可以用于响应于上下文切换事件来存储或恢复计数器值和状态机配置。

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