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1. 发明授权

US08275964B2 Hardware support for collecting performance counters directly to memory 失效
标题翻译：硬件支持将性能计数器直接收集到内存中
公开(公告)号：US08275964B2
公开(公告)日：2012-09-25
申请号：US12684172
申请日：2010-01-08
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F11/348 , G06F2201/88
摘要： Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.
摘要翻译：在一个方面，在性能计数器直接收集到存储器的硬件支持可以包括多个性能计数器，可操作以收集一个或多个所选活动的一个或多个计数。第一存储元件可以用于存储存储器位置的地址。第二存储元件可以用于存储指示硬件是否应该开始复制的值。状态机可操作用于检测第二存储元件中的值，并且触发多个性能计数器中所选择的一个或多个性能计数器中的数据的硬件复制到其地址存储在第一存储元件中的存储单元。

2. 发明授权

US08275954B2 Using DMA for copying performance counter data to memory 失效
标题翻译：使用DMA将性能计数器数据复制到存储器
公开(公告)号：US08275954B2
公开(公告)日：2012-09-25
申请号：US12684367
申请日：2010-01-08
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F13/28 , G06F11/34 , G06F2201/88
摘要： A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.
摘要翻译：用于复制性能计数器数据的设备包括将直接存储器访问（DMA）单元连接到多个硬件性能计数器和存储器设备的硬件路径。软件为DMA单元准备一个注入数据包来执行复制，而软件可以执行其他任务。在一个方面，准备注射分组的软件在收集硬件性能计数器数据的核心以外的处理核上运行。

3. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

4. 发明授权

US08621167B2 Using DMA for copying performance counter data to memory 失效
标题翻译：使用DMA将性能计数器数据复制到存储器
公开(公告)号：US08621167B2
公开(公告)日：2013-12-31
申请号：US13446467
申请日：2012-04-13
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/00
CPC分类号： G06F13/28 , G06F11/34 , G06F2201/88
摘要： A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.
摘要翻译：用于复制性能计数器数据的设备包括将直接存储器访问（DMA）单元连接到多个硬件性能计数器和存储器设备的硬件路径。软件为DMA单元准备一个注入数据包来执行复制，而软件可以执行其他任务。在一个方面，准备注射分组的软件在收集硬件性能计数器数据的核心以外的处理核上运行。

5. 发明申请

US20110173403A1 USING DMA FOR COPYING PERFORMANCE COUNTER DATA TO MEMORY 失效
标题翻译：使用DMA将性能计数器数据复制到存储器
公开(公告)号：US20110173403A1
公开(公告)日：2011-07-14
申请号：US12684367
申请日：2010-01-08
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/16 , G06F13/28 , G06F3/00
CPC分类号： G06F13/28 , G06F11/34 , G06F2201/88
摘要： A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.
摘要翻译：用于复制性能计数器数据的设备包括将直接存储器访问（DMA）单元连接到多个硬件性能计数器和存储器设备的硬件路径。软件为DMA单元准备一个注入数据包来执行复制，而软件可以执行其他任务。在一个方面，准备注射分组的软件在收集硬件性能计数器数据的核心以外的处理核上运行。

6. 发明申请

US20110173402A1 HARDWARE SUPPORT FOR COLLECTING PERFORMANCE COUNTERS DIRECTLY TO MEMORY 失效
标题翻译：硬件支持直接收集性能计数器
公开(公告)号：US20110173402A1
公开(公告)日：2011-07-14
申请号：US12684172
申请日：2010-01-08
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/16
CPC分类号： G06F11/348 , G06F2201/88
摘要： Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.
摘要翻译：在一个方面，在性能计数器直接收集到存储器的硬件支持可以包括多个性能计数器，可操作以收集一个或多个所选活动的一个或多个计数。第一存储元件可以用于存储存储器位置的地址。第二存储元件可以用于存储指示硬件是否应该开始复制的值。状态机可操作用于检测第二存储元件中的值，并且触发多个性能计数器中所选择的一个或多个性能计数器中的数据的硬件复制到其地址存储在第一存储元件中的存储单元。

7. 发明申请

US20120198118A1 USING DMA FOR COPYING PERFORMANCE COUNTER DATA TO MEMORY 失效
标题翻译：使用DMA将性能计数器数据复制到存储器
公开(公告)号：US20120198118A1
公开(公告)日：2012-08-02
申请号：US13446467
申请日：2012-04-13
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F13/36
CPC分类号： G06F13/28 , G06F11/34 , G06F2201/88
摘要： A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.
摘要翻译：用于复制性能计数器数据的设备包括将直接存储器访问（DMA）单元连接到多个硬件性能计数器和存储器设备的硬件路径。软件为DMA单元准备一个注入数据包来执行复制，而软件可以执行其他任务。在一个方面，准备注射分组的软件在收集硬件性能计数器数据的核心以外的处理核上运行。

8. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

9. 发明申请

US20120210172A1 MULTIPROCESSOR SWITCH WITH SELECTIVE PAIRING 失效
标题翻译：具有选择性配对的多处理器开关
公开(公告)号：US20120210172A1
公开(公告)日：2012-08-16
申请号：US13027882
申请日：2011-02-15
申请人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
发明人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
IPC分类号： G06F11/07
CPC分类号： G06F11/1641 , G06F11/1654 , G06F2201/845
摘要： System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory “nest” (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus.
摘要翻译：用于多处理系统的系统，方法和计算机程序产品，以提供处理器核心的选择性配对，以提高处理可靠性。提供选择性配对设施，其选择性地连接，即配对多个微处理器或处理器核，以提供一个高度可靠的线程（或线程组）。每个成对的微处理器或处理器核心提供一个高度可靠的线程，用于高可靠性与诸如存储器“嵌套”（或存储器层级），可选系统控制器和可选中断控制器的系统组件连接，可选的I / O或外设设备等。存储器套件通过开关或总线连接到选择性配对设施。

10. 发明申请

US20120210164A1 SCHEDULER FOR MULTIPROCESSOR SYSTEM SWITCH WITH SELECTIVE PAIRING 有权
标题翻译：具有选择性配对的多处理器系统开关调度器
公开(公告)号：US20120210164A1
公开(公告)日：2012-08-16
申请号：US13027960
申请日：2011-02-15
申请人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
发明人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
IPC分类号： G06F11/07
CPC分类号： G06F11/1641 , G06F11/165 , G06F2201/845
摘要： System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.
摘要翻译：用于在具有选择性配对处理器核心的多处理系统中调度线程的系统，方法和计算机程序产品，用于提高处理可靠性。提供选择性配对设施，其选择性地连接，即配对多个微处理器或处理器核，以提供一个高度可靠的线程（或线程组）。该方法配置选择性配对设施以使用检查提供一个高度可靠的线程以实现高可靠性，并将线程分配给相应的处理器核心，指示需要进行硬件检查。该方法配置选择性配对工具以提供多个独立核心，并将线程分配给相应的处理器核心，指示固有的弹性。

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