专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07993950B2 System and method of encapsulation 有权
标题翻译：系统和封装方法
公开(公告)号：US07993950B2
公开(公告)日：2011-08-09
申请号：US12266457
申请日：2008-11-06
申请人： Joseph Damian Gordon Lacey , Mickael Renault , Vikram Joshi , James F. Bobey , Robertus P. Van Kampen
发明人： Joseph Damian Gordon Lacey , Mickael Renault , Vikram Joshi , James F. Bobey , Robertus P. Van Kampen
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： B81C1/00333 , B81C2203/0145 , B81C2203/0154
摘要： Embodiments discussed herein generally include methods of fabricating MEMS devices within a structure. The MEMS device may be formed in a cavity above the structure, and additional metallization may occur above the MEMS device. The cavity may be formed by depositing an encapsulating layer over the sacrificial layers that enclose the MEMS device. The encapsulating layer may then be etched to expose portions of the sacrificial layers. The sacrificial layers are exposed because they extend through the sidewalls of the encapsulating layer. Therefore, no release holes are etched through the top of the encapsulating layer. An etchant then removes the sacrificial layers to free the MEMS device and form the cavity and an opening through the sidewall of the encapsulating layer. Another encapsulating layer may then be deposited to seal the cavity and the opening.
摘要翻译：本文讨论的实施例通常包括在结构内制造MEMS器件的方法。 MEMS器件可以形成在结构上方的空腔中，并且可以在MEMS器件上方发生额外的金属化。空腔可以通过在包围MEMS器件的牺牲层上沉积封装层来形成。然后可以蚀刻封装层以暴露部分牺牲层。牺牲层被暴露，因为它们延伸穿过封装层的侧壁。因此，没有通过封装层的顶部蚀刻释放孔。然后，蚀刻剂去除牺牲层以释放MEMS器件并形成空腔和通过封装层的侧壁的开口。然后可以沉积另外的封装层以密封空腔和开口。

2. 发明授权

US07867886B2 Method of enclosing a micro-electromechanical element 有权
标题翻译：封闭微机电元件的方法
公开(公告)号：US07867886B2
公开(公告)日：2011-01-11
申请号：US12085428
申请日：2006-11-22
申请人： Charles Gordon Smith , Robertus P. Van Kampen
发明人： Charles Gordon Smith , Robertus P. Van Kampen
IPC分类号： H01L21/445 , B81C1/00 , H01L23/525
CPC分类号： B81C1/00333 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method, in a complementary metal oxide semiconductor fabrication process, of creating a layered housing containing a micro-electromechanical system device, the method comprising the steps of providing a cavity in at least one layer of the housing, the cavity being accessible through via holes in a layer of insulating material deposited thereon, and the layer of insulating material being covered by a thin film layer of conductive material. The method further comprises the step of hydrophobically treating at least a portion of the inner surface of the cavity. Finally the method comprises the steps of submerging the wafer in an electroplating solution and electroplating a conductive layer onto the thin film layer of conductive material such that the cavity remains free of electroplating solution.
摘要翻译：在互补金属氧化物半导体制造工艺中，制造包含微机电系统器件的分层壳体的方法，所述方法包括以下步骤：在所述壳体的至少一层中提供空腔，所述空腔可通过通孔在其上沉积的绝缘材料层中，并且绝缘材料层被导电材料的薄膜层覆盖。该方法还包括对空腔的内表面的至少一部分进行疏水处理的步骤。最后，该方法包括以下步骤：将晶片浸入电镀溶液中，并将导电层电镀到导电材料的薄膜层上，使得空腔保持不含电镀溶液。

3. 发明申请

US20100038731A1 NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：US20100038731A1
公开(公告)日：2010-02-18
申请号：US12441254
申请日：2006-11-02
申请人： Robertus P. Van Kampen , Robert Kazinczi
发明人： Robertus P. Van Kampen , Robert Kazinczi
IPC分类号： H01L29/84 , H01L21/3205
CPC分类号： H01H59/0009 , B81C1/0015 , B81C2201/014 , B81C2201/0176 , G11C23/00 , H01H51/12
摘要： A non-volatile memory device and method of manufacturing a non-volatile micro-electromechanical memory cell. The method comprises the first step of depositing a first layer of sacrificial material on a substrate by use of Atomic Layer Deposition The second step of the method is providing a cantilever (101) over at least a portion of the first layer of sacrificial material. The third step is depositing, by use of Atomic Layer Deposition, a second layer of sacrificial material over the first layer of sacrificial material and over a portion of the cantilever such that a portion of the cantilever is surrounded by sacrificial material. The fourth step is providing a further layer material (107) which covers at least a portion of the second layer of sacrificial material. Finally, the last step is etching away the sacrificial material surrounding the cantilever, thereby defining a cavity (102) in which the cantilever is suspended.
摘要翻译：一种非易失性存储器件和制造非易失性微机电存储单元的方法。该方法包括通过使用原子层沉积在衬底上沉积第一层牺牲材料的第一步骤。该方法的第二步是在第一层牺牲材料的至少一部分上提供悬臂（101）。第三步骤是通过使用原子层沉积在第一层牺牲材料上并在悬臂的一部分上沉积第二层牺牲材料，使得悬臂的一部分被牺牲材料包围。第四步是提供覆盖牺牲材料的第二层的至少一部分的另外的层材料（107）。最后，最后一步是蚀刻掉围绕悬臂的牺牲材料，由此限定悬臂悬挂在其中的空腔（102）。

4. 发明申请

US20090298215A1 Method of Enclosing a Micro-Electromechanical Element 有权
标题翻译：封闭微机电元件的方法
公开(公告)号：US20090298215A1
公开(公告)日：2009-12-03
申请号：US12085428
申请日：2006-11-22
申请人： Charles Gordon Smith , Robertus P. Van Kampen
发明人： Charles Gordon Smith , Robertus P. Van Kampen
IPC分类号： H01L21/50
CPC分类号： B81C1/00333 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method, in a complementary metal oxide semiconductor fabrication process, of creating a layered housing containing a micro-electromechanical system device, the method comprising the steps of providing a cavity in at least one layer of the housing, the cavity being accessible through via holes in a layer of insulating material deposited thereon, and the layer of insulating material being covered by a thin film layer of conductive material. The method further comprises the step of hydrophobically treating at least a portion of the inner surface of the cavity. Finally the method comprises the steps of submerging the wafer in an electroplating solution and electroplating a conductive layer onto the thin film layer of conductive material such that the cavity remains free of electroplating solution.
摘要翻译：在互补金属氧化物半导体制造工艺中，制造包含微机电系统器件的分层壳体的方法，所述方法包括以下步骤：在所述壳体的至少一层中提供空腔，所述空腔可通过通孔在其上沉积的绝缘材料层中，并且绝缘材料层被导电材料的薄膜层覆盖。该方法还包括对空腔的内表面的至少一部分进行疏水处理的步骤。最后，该方法包括以下步骤：将晶片浸入电镀溶液中，并将导电层电镀到导电材料的薄膜层上，使得空腔保持不含电镀溶液。

5. 发明申请

US20090275163A1 System and Method of Encapsulation 有权
标题翻译：封装的系统和方法
公开(公告)号：US20090275163A1
公开(公告)日：2009-11-05
申请号：US12266457
申请日：2008-11-06
申请人： Joseph Damian Gordon Lacey , Mickael Renault , Vikram Joshi , James F. Bobey , Robertus P. Van Kampen
发明人： Joseph Damian Gordon Lacey , Mickael Renault , Vikram Joshi , James F. Bobey , Robertus P. Van Kampen
IPC分类号： H01L21/56
CPC分类号： B81C1/00333 , B81C2203/0145 , B81C2203/0154
摘要： Embodiments discussed herein generally include methods of fabricating MEMS devices within a structure. The MEMS device may be formed in a cavity above the structure, and additional metallization may occur above the MEMS device. The cavity may be formed by depositing an encapsulating layer over the sacrificial layers that enclose the MEMS device. The encapsulating layer may then be etched to expose portions of the sacrificial layers. The sacrificial layers are exposed because they extend through the sidewalls of the encapsulating layer. Therefore, no release holes are etched through the top of the encapsulating layer. An etchant then removes the sacrificial layers to free the MEMS device and form the cavity and an opening through the sidewall of the encapsulating layer. Another encapsulating layer may then be deposited to seal the cavity and the opening.
摘要翻译：本文讨论的实施例通常包括在结构内制造MEMS器件的方法。 MEMS器件可以形成在结构上方的空腔中，并且可以在MEMS器件上方发生额外的金属化。空腔可以通过在包围MEMS器件的牺牲层上沉积封装层来形成。然后可以蚀刻封装层以暴露部分牺牲层。牺牲层被暴露，因为它们延伸穿过封装层的侧壁。因此，没有通过封装层的顶部蚀刻释放孔。然后，蚀刻剂去除牺牲层以释放MEMS器件并形成空腔和通过封装层的侧壁的开口。然后可以沉积另外的封装层以密封空腔和开口。

6. 发明申请

US20090268503A1 NON-VOLATILE MEMORY BITCELL 审中-公开
标题翻译：非易失性存储器BITCELL
公开(公告)号：US20090268503A1
公开(公告)日：2009-10-29
申请号：US12441121
申请日：2007-09-13
申请人： Cornelius Petrus Elisabeth Schepens , Robertus P. Van Kampen
发明人： Cornelius Petrus Elisabeth Schepens , Robertus P. Van Kampen
IPC分类号： G11C5/06 , G11C11/50
CPC分类号： G11C23/00 , G11C13/004 , G11C2013/0042
摘要： A non-volatile memory bitcell which comprises a first bistable cantilever module and a second bistable cantilever modules. The bistable cantilever modules have a shared output terminal and each has an input terminal and two actuating terminals. The first and second cantilever modules are arranged such that their states are complementary. The memory bitcell further includes buffering means arranged to prevent the flow of current from the shared output terminal and further arranged to indicate the states of the first and second cantilever modules.
摘要翻译：一种非易失性存储器位单元，包括第一双稳态悬臂模块和第二双稳态悬臂模块。双稳态悬臂模块具有共享输出端子，每个端子均具有输入端子和两个驱动端子。第一和第二悬臂模块被布置成使得它们的状态是互补的。存储位单元还包括缓冲装置，其被布置成防止来自共享输出端子的电流流动，并进一步布置成指示第一和第二悬臂模块的状态。

7. 发明申请

US20090134522A1 Micro-Electromechanical System Memory Device and Method of Making the Same 审中-公开
标题翻译：微机电系统存储器及其制作方法
公开(公告)号：US20090134522A1
公开(公告)日：2009-05-28
申请号：US12085506
申请日：2006-11-22
申请人： Charles Gordon Smith , Robert Kazinczi , Robertus P. Van Kampen
发明人： Charles Gordon Smith , Robert Kazinczi , Robertus P. Van Kampen
IPC分类号： H01L29/45 , H01L21/441
CPC分类号： B81C1/00666 , B81B3/001 , B81B2203/0118 , B81C2201/0109 , G11C23/00
摘要： A method of manufacturing a non-volatile memory bitcell comprises the steps of depositing a first layer of conductive material on a substrate and patterning and etching the first layer of conductive material to form three non-linearly disposed electrodes. The method also comprises the steps of depositing a first layer of sacrificial material on the electrodes and the substrate and providing an elongate cantilever structure on the first layer of sacrificial material such that the cantilever structure and at least a portion of each electrode overlap each other. The method also includes the steps of depositing a second layer of sacrificial material on the cantilever structure and the first layer of sacrificial material and providing a capping layer on the second layer of sacrificial material and providing holes in the capping layer such that at least a portion of the second layer of sacrificial material is exposed. Finally, the method provides the step of removing the first and second layers of sacrificial material through the holes provided in the capping layer, thereby defining a cavity in which the cantilever structure is suspended.
摘要翻译：一种制造非易失性存储器位单元的方法包括以下步骤：将第一层导电材料沉积在衬底上，并对第一层导电材料进行图案化和蚀刻以形成三个非线性布置的电极。该方法还包括以下步骤：在电极和衬底上沉积牺牲材料的第一层，并在第一牺牲材料层上提供细长的悬臂结构，使得悬臂结构和每个电极的至少一部分彼此重叠。该方法还包括以下步骤：将第二层牺牲材料沉积在悬臂结构和第一牺牲材料层上，并在牺牲材料的第二层上提供覆盖层，并在封盖层中提供孔，使得至少一部分的第二层牺牲材料被暴露。最后，该方法提供了通过设置在覆盖层中的孔去除第一层和第二层牺牲材料的步骤，从而限定悬臂悬臂结构的空腔。

8. 发明授权

US5812047A Offset-free resistor geometry for use in piezo-resistive pressure sensor 失效
标题翻译：用于压阻式压力传感器的无偏移电阻几何形状
公开(公告)号：US5812047A
公开(公告)日：1998-09-22
申请号：US800437
申请日：1997-02-18
申请人： Robertus P. van Kampen
发明人： Robertus P. van Kampen
IPC分类号： G01L9/00 , G01L1/22
CPC分类号： G01L9/0054
摘要： An improved resistor and connection region structure in which the geometries of the connection regions for a pair of radial resistors correspond to the connection region geometries for a pair of tangential resistors, thus inherently eliminating the need for varying connection regions to compensate for offset. In particular, the radial resistors are formed by placing two legs in parallel with each other and connecting those legs in series on opposite sides of the membrane, with the connection region on the interior of the membrane. The tangential resistors, on the other hand, are formed on the opposite sides by placing two legs in series with each other and connecting those legs in series, with an interior connection region connecting them.
摘要翻译：一种改进的电阻器和连接区域结构，其中一对径向电阻器的连接区域的几何形状对应于一对切向电阻器的连接区域几何形状，因此固有地消除了对变化的连接区域以补偿偏移的需要。特别地，径向电阻器通过将两个腿彼此平行地放置并且将这些腿串联连接在膜的相对侧上而形成，其中膜的内部上的连接区域。另一方面，切向电阻器通过将两个腿彼此串联并且将这些腿串联连接并且连接它们的内部连接区域而形成在相对侧上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式