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1. 发明授权

US07334204B2 System for avoiding false path pessimism in estimating net delay for an integrated circuit design 失效
标题翻译：用于在估计集成电路设计的网络延迟方面避免虚假路径悲观的系统
公开(公告)号：US07334204B2
公开(公告)日：2008-02-19
申请号：US11324082
申请日：2005-12-29
申请人： Weiqing Guo , Sandeep Bhutani , Ivan Pavisic
发明人： Weiqing Guo , Sandeep Bhutani , Ivan Pavisic
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5031
摘要： A system for estimating stage delay in an integrated circuit design includes steps of receiving as input an integrated circuit design including a single stage having at least two inputs, an output, and an interconnect connected to the output; calculating a separate interconnect delay for the interconnect as a function of an input ramptime for each of the inputs; adding a gate delay of each of the inputs to the separate interconnect delay calculated as a function of the input ramptime to estimate a stage delay for each of the inputs; and generating as output the stage delay for each of the inputs.
摘要翻译：一种用于估计集成电路设计中的级延迟的系统包括以下步骤：接收作为输入的集成电路设计，其包括具有至少两个输入的单级，输出和连接到所述输出的互连; 计算互连的单独互连延迟作为每个输入的输入衰减的函数; 将每个输入的门延迟添加到作为输入衰减时间的函数计算的单独互连延迟，以估计每个输入的级延迟; 并为每个输入产生阶段延迟作为输出。

2. 发明授权

US07082583B2 Method for reducing a parasitic graph in moment computation in VLSI systems 失效
标题翻译：减少VLSI系统中力矩计算寄生图的方法
公开(公告)号：US07082583B2
公开(公告)日：2006-07-25
申请号：US10301069
申请日：2002-11-20
申请人： Weiqing Guo , Sandeep Bhutani
发明人： Weiqing Guo , Sandeep Bhutani
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.
摘要翻译：用于VLSI电路的互连延迟分析的改进方法通过消除图中的一个或多个节点来减少用于时刻计算的寄生图。基于节点的程度来执行消除处理。通过以这种方式消除节点，显着地减少了计算复杂度。通过这种消除过程，电阻环和交叉环也可以解决。使用寄生图上的深度优先搜索方法优化消除节点的顺序，进一步降低计算复杂度。该方法提供了一致的功能接口，适用于不同的电路模型结构。此外，该方法考虑了互连之间的耦合电容。

3. 发明授权

US06990420B2 Method of estimating a local average crosstalk voltage for a variable voltage output resistance model 失效
标题翻译：估计可变电压输出电阻模型的局部平均串扰电压的方法
公开(公告)号：US06990420B2
公开(公告)日：2006-01-24
申请号：US10842879
申请日：2004-05-10
申请人： Weiqing Guo , Sandeep Bhutani , Oian Cui
发明人： Weiqing Guo , Sandeep Bhutani , Oian Cui
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method includes steps of: (a) receiving as input a waveform of a transient signal as a function of time for an aggressor net; (b) finding a peak value of the waveform and a corresponding peak time of the waveform propagated from the aggressor net to a victim net; (c) defining a selected time interval within the waveform at the victim net that includes the peak value and excludes features of the waveform not associated with the peak value wherein the selected time interval begins at a first time and ends at a second time; (d) calculating a weighted value of a function of the waveform at the first time and the second time; (e) calculating a local average value of the waveform as a function of the peak value and the weighted value; and (f) generating as output the local average value of the waveform.
摘要翻译：一种方法包括以下步骤：（a）作为输入接收作为侵入网的时间的函数的瞬态信号的波形; （b）找出波形的峰值和从侵略网传播到受害网的波形的相应峰值时间; （c）在包括峰值的受害网络的波形内定义选定的时间间隔，并且排除与峰值不相关联的波形的特征，其中所选择的时间间隔在第一时间开始并在第二时间结束; （d）计算第一次和第二次的波形的函数的加权值; （e）计算作为峰值和加权值的函数的波形的局部平均值; 和（f）产生波形的局部平均值作为输出。

4. 发明授权

US06845348B1 Driver waveform modeling with multiple effective capacitances 失效
标题翻译：具有多个有效电容的驱动器波形建模
公开(公告)号：US06845348B1
公开(公告)日：2005-01-18
申请号：US09814417
申请日：2001-03-21
申请人： Prasad Subbarao , Sandeep Bhutani , Charutosh Dixit , Prabhakaran Krishnamurthy
发明人： Prasad Subbarao , Sandeep Bhutani , Charutosh Dixit , Prabhakaran Krishnamurthy
IPC分类号： G06F17/10 , G06F17/50 , G06F15/60
CPC分类号： G06F17/5036
摘要： A method for modeling the output waveform of a cell driving a resistance-capacitance network includes multiple effective capacitances. A method of calculating Thevenin parameters includes the steps of (a) initializing estimates of effective capacitances Ceff1 and Ceff2, of a switching threshold delay t0, and of a slope delay deltat; (b) solving ramp response equations for t0 and deltat as a function of Ceff1 and Ceff2; (c) comparing the estimates of t0 and deltat with solutions for t0 and deltat found in step (b); and (d) replacing the estimates of t0 and deltat with the solutions for t0 and deltat if the solutions for t0 and deltat have not converged to the estimates of t0 and deltat.
摘要翻译：用于建模驱动电阻 - 电容网络的单元的输出波形的方法包括多个有效电容。计算戴维宁参数的方法包括以下步骤：（a）初始化切换阈值延迟t0的有效电容Ceff1和Ceff2的估计值以及斜率延迟增量; （b）求解作为Ceff1和Ceff2函数的t0和deltat的斜率响应方程; （c）将t0和deltat的估计与步骤（b）中发现的t0和deltat的解决方案进行比较; 和（d）如果t0和deltat的解不会与t0和deltat的估计值相关，则用t0和deltat的解来替换t0和deltat的估计。

5. 发明申请

US20110258587A1 SIGNAL DELAY SKEW REDUCTION SYSTEM 失效
标题翻译：信号延迟减少系统
公开(公告)号：US20110258587A1
公开(公告)日：2011-10-20
申请号：US13173855
申请日：2011-06-30
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，提供了一种用于减少信号延迟偏差的系统和方法。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括：接收在组件之间具有组件和连接路径的初始网表; 识别所述初始网表中的第一连接路径，其包括在所述初始网表中的第二连接路径中不存在等效路径片段的路径片段; 生成偏差校正网表，其中所述第二连接路径被重新路由以具有等同于所述第一连接路径的路径片段的路径片段; 并输出偏差校正的网表。

6. 发明申请

US20090187873A1 SIGNAL DELAY SKEW REDUCTION SYSTEM 有权
标题翻译：信号延迟减少系统
公开(公告)号：US20090187873A1
公开(公告)日：2009-07-23
申请号：US12015925
申请日：2008-01-17
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，公开了一种用于减小信号延迟偏差的系统。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括接收包括组件之间的组件和连接路径的初始网表。该方法还包括识别在初始网表中的第一连接路径中的一个或多个偏斜影响特征，其在初始网表中的第二连接路径中缺少对应的偏斜影响特征。该方法还包括生成偏差校正网表，其中第二连接路径包括与第一连接路径的相应的一个或多个相加的偏斜影响特征。该方法还包括输出经偏斜校正的网表。

7. 发明申请

US20080163145A1 PROBABILISTIC NOISE ANALYSIS 失效
标题翻译：概率噪声分析
公开(公告)号：US20080163145A1
公开(公告)日：2008-07-03
申请号：US12046169
申请日：2008-03-11
申请人： Payman Zarkesh-Ha , Sandeep Bhutani , Weiqing Guo
发明人： Payman Zarkesh-Ha , Sandeep Bhutani , Weiqing Guo
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.
摘要翻译：一种确定来自侵略者网络的电压是否超过集成电路设计中的受害网络设计的电压阈值的方法。计算受害者网络上侵略者网络的概率噪声。根据电压阈值检查概率噪声，当概率噪声不超过电压阈值时，通过受害网设计。当概率噪声超过阈值时，计算所需的故障平均时间的有效噪声，并根据电压阈值检查有效噪声。当有效噪声不超过电压阈值时，受害者网络设计通过，当有效噪声超过阈值时失败。

8. 发明授权

US07260801B2 Delay computation speed up and incrementality 有权
标题翻译：延迟计算加速和增量
公开(公告)号：US07260801B2
公开(公告)日：2007-08-21
申请号：US11192526
申请日：2005-07-29
申请人： Sandeep Bhutani , Qian Cui , Weiqing Guo
发明人： Sandeep Bhutani , Qian Cui , Weiqing Guo
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method of computing output delay in a mathematical model of an integrated circuit by sorting cells of original design of an the integrated circuit in a topological order. The original output delays for the sorted cells in the original design are computed in the topological order, to produce original output ramp times. The original output ramp times are propagated and original output delays are computed, and the original output ramp time and original output load for each cell is stored. The cells of the original design are modified to produce a modified design. For each modified cell in the topological order, a new output delay and a new output ramp time are computed and compared to the original output ramp time on the modified cell. When the new output ramp time substantially equals the original output ramp time for a modified cell, the calculations of the modified output ramp time for cells that are further down in the topological order are stopped. Otherwise the calculations of the modified output ramp time for cells that are further down in the topological order are continued until a cell is reached where the new output ramp time substantially equals the original output ramp time.
摘要翻译：通过以拓扑顺序对集成电路的原始设计的单元进行排序来计算集成电路的数学模型中的输出延迟的方法。原始设计中排序单元格的原始输出延迟以拓扑顺序计算，以产生原始输出斜坡时间。原始输出斜坡时间被传播并且计算出原始输出延迟，并且存储每个单元的原始输出斜坡时间和原始输出负载。原始设计的单元被修改以产生修改的设计。对于每个修改的单元，按拓扑顺序，计算新的输出延迟和新的输出斜坡时间，并将其与修改单元上的原始输出斜坡时间进行比较。当新的输出斜坡时间基本上等于修改的单元的原始输出斜坡时间时，停止按拓扑顺序进一步降低的单元的修改的输出斜坡时间的计算。否则，继续按照拓扑顺序进一步降低的单元的修改的输出斜坡时间的计算，直到达到单元，其中新的输出斜坡时间基本上等于原始输出斜坡时间。

9. 发明申请

US20060190859A1 Negative bias temperature instability modeling 有权
标题翻译：负偏温度不稳定性模型
公开(公告)号：US20060190859A1
公开(公告)日：2006-08-24
申请号：US11061581
申请日：2005-02-18
申请人： Qian Cui , Sandeep Bhutani
发明人： Qian Cui , Sandeep Bhutani
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： A method for accounting for negative bias temperature instability in a rise delay of a circuit design, the method comprising the steps of create a cell and net model library with original rise numbers, construct the circuit design from the cell and net models, for each cell and net in the circuit design, calculate an original rise delay, apply a negative bias temperature instability model to determine a parameter shift, determine a new rise number from the parameter shift, and calculate a new rise delay by original rise delay*(original rise number)/(new rise number).
摘要翻译：一种用于计算电路设计的上升延迟中的负偏压温度不稳定性的方法，所述方法包括以下步骤：创建具有原始上升数的单元和网模型库，为每个单元构建单元和网模型的电路设计并在电路设计中，计算原始上升延迟，应用负偏置温度不稳定模型确定参数偏移，从参数偏移确定新的上升数，并通过原始上升延迟计算新的上升延迟*（原始上升数字）/（新上升数）。

10. 发明授权

US07069178B2 Method of predicting quiescent current variation of an integrated circuit die from a process monitor derating factor 有权
公开(公告)号：US07069178B2
公开(公告)日：2006-06-27
申请号：US10955168
申请日：2004-09-29
申请人： Qian Cui , Sandeep Bhutani
发明人： Qian Cui , Sandeep Bhutani
IPC分类号： G06F3/01
CPC分类号： G01R31/3008
摘要： In exemplary embodiments, a method and computer program product for predicting quiescent current variation of an integrated circuit die include steps of: (a) receiving as input a value of a derating factor from a process monitor cell on an integrated circuit die and an on-chip variation of the derating factor; (b) constructing a curve fitting formula for estimating a quiescent current of the integrated circuit die as a function of the derating factor; (c) calculating minimum and maximum values of the quiescent current from the curve fitting formula, the value of the derating factor from the process monitor cell, and the on-chip variation of the derating factor to generate an estimate of minimum and maximum values for the quiescent current; and (d) generating as output the estimated minimum and maximum values of the quiescent current.

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