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1. 发明授权

US08239813B2 Method and apparatus for balancing signal delay skew 失效
标题翻译：信号延迟偏移平衡的方法和装置
公开(公告)号：US08239813B2
公开(公告)日：2012-08-07
申请号：US13173855
申请日：2011-06-30
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，提供了一种用于减少信号延迟偏差的系统和方法。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括：接收在组件之间具有组件和连接路径的初始网表; 识别所述初始网表中的第一连接路径，其包括在所述初始网表中的第二连接路径中不存在等效路径片段的路径片段; 生成偏差校正网表，其中所述第二连接路径被重新路由以具有等同于所述第一连接路径的路径片段的路径片段; 并输出偏差校正的网表。

2. 发明申请

US20050010884A1 Optimizing IC clock structures by minimizing clock uncertainty 有权
标题翻译：通过最小化时钟不确定性优化IC时钟结构
公开(公告)号：US20050010884A1
公开(公告)日：2005-01-13
申请号：US10616623
申请日：2003-07-10
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G01R31/30 , G06F1/10 , G06F9/45
CPC分类号： G06F1/10 , G01R31/3016
摘要： Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a predetermined character along the first path. A second path from the launching cell toward the clock source is back-traced to a predetermined marked cell. Clock uncertainty is calculated based on the portion of the first path from the predetermined marked cell to the receiving cell. Clock uncertainty is calculated if a slack does not exceed a margin value. In one embodiment, a clock net in the form of a tree is optimized by forcing a first buffer to the center of gravity of a plurality of buffers having nets without timing violations to maximize a common path from the root to the forced buffer and minimize the non-common paths from the forced buffer to the leaves, thereby minimizing clock uncertainty.
摘要翻译：通过从接收单元向时钟源的后向跟踪第一路径并且沿着第一路径标记具有预定字符的每个单元来估计接收小区和网络的启动小区之间的时钟不确定性。从启动单元向时钟源的第二条路径被追溯到预定的标记单元。基于从预定标记小区到接收小区的第一路径的部分来计算时钟不确定性。如果松弛不超过余量值，则计算时钟不确定度。在一个实施例中，通过将第一缓冲器强制为具有网络的多个缓冲器的重心而没有定时违反来最大化从根到强制缓冲器的公共路径，使得最小化从强制缓冲区到叶片的非公共路径，从而最小化时钟不确定性。

3. 发明授权

US06691283B1 Optimization of comparator architecture 失效
标题翻译：比较器架构优化
公开(公告)号：US06691283B1
公开(公告)日：2004-02-10
申请号：US10017792
申请日：2001-12-12
申请人： Sergej B. Gashkov , Alexander E. Andreev , Aiguo Lu
发明人： Sergej B. Gashkov , Alexander E. Andreev , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F7/02 , G06F17/5045
摘要： A circuit embodied in an integrated circuit is characterized by an architecture having a minimal depth defined by a recursive expansion of output functions h_n=OR(h_k, AND(v_k, h_{n−k})) and v_n=AND(v_k, v{n−k}), where k=F_l and n−k=F_{l−1}, satisfies F_l
摘要翻译：具体化在集成电路中的电路的特征在于具有通过输出函数h_n = OR（h_k，AND（v_k，h_ {nk}））和v_n = AND（v_k，v_nk}）的递归展开定义的最小深度的架构 }），其中k = F_l和nk = F_ {1-1}，满足F_l

4. 发明授权

US06470487B1 Parallelization of resynthesis 有权
标题翻译：再合成平行化
公开(公告)号：US06470487B1
公开(公告)日：2002-10-22
申请号：US09842350
申请日：2001-04-25
申请人： Andrej A. Zolotykh , Elyar E. Gasanov , Ivan Pavisic , Aiguo Lu
发明人： Andrej A. Zolotykh , Elyar E. Gasanov , Ivan Pavisic , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A method for resynthesizing a design of an integrated circuit using a parallel processing mode. A single processing mode is entered by activating a main thread and locking a semaphore associated with the main thread. The design of the integrated circuit is resynthesized using the main thread. Tasks to be accomplished in the parallel processing mode are identified. The semaphore associated with the main thread is unlocked, and the operation of the single processing mode is ceased. Ordinal threads are activated by unlocking a semaphore associated with each ordinal thread. The tasks are processed in parallel by assigning the tasks to the ordinal threads and the main thread. Upon completion of one of the assigned tasks by one of the ordinal threads, it is determined whether an additional task remains to be assigned. In the case where the additional task remains, the additional task is assigned to the completed one of the ordinal threads. In the case where the additional task does not remain, the completed one of the ordinal threads is inactivated. Upon inactivation of all of the ordinal threads, a return is made to the single processing mode, with the ordinal threads remaining inactive unless and until the main thread identifies more tasks to be accomplished in the parallel processing mode.
摘要翻译：一种使用并行处理模式重新合成集成电路的设计的方法。通过激活主线程并锁定与主线程相关联的信号量来输入单个处理模式。集成电路的设计使用主线重新合成。识别以并行处理模式完成的任务。与主线程相关联的信号量被解锁，并且停止单处理模式的操作。通过解锁与每个顺序线程相关联的信号量激活有序线程。通过将任务分配给顺序线程和主线程，并行处理任务。在通过其中一个顺序线程完成一个分配的任务之后，确定是否还有一个额外的任务被分配。在附加任务保留的情况下，附加任务被分配给完成的一个序数线程。在附加任务不存在的情况下，完成的一个顺序线程将被禁用。在所有顺序线程失效后，返回到单个处理模式，顺序线程保持不活动，除非主线程在并行处理模式下识别要完成的更多任务。

5. 发明申请

US20060190886A1 Optimizing IC clock structures by minimizing clock uncertainty 失效
标题翻译：通过最小化时钟不确定性优化IC时钟结构
公开(公告)号：US20060190886A1
公开(公告)日：2006-08-24
申请号：US11402146
申请日：2006-04-11
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G01R31/3016
摘要： A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.
摘要翻译：提供了一种用于优化具有由驱动器引脚限定的根和由驱动引脚限定的多个叶的树形式的时钟网的过程。该过程包括将第一缓冲区强制到多个叶片的重心，插入一组第二缓冲器，使得每个叶片被插入的缓冲器驱动而没有定时违反，并且将第一缓冲器移动到该集合的重心的第二缓冲区。

6. 发明授权

US06553551B1 Timing recomputation 有权
标题翻译：定时重新计算
公开(公告)号：US06553551B1
公开(公告)日：2003-04-22
申请号：US09841825
申请日：2001-04-25
申请人： Andrej A. Zolotykh , Elyar E. Gasanov , Ivan Pavisic , Aiguo Lu
发明人： Andrej A. Zolotykh , Elyar E. Gasanov , Ivan Pavisic , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5031
摘要： A method of computing timing delays of timing edges of a path of an integrated circuit design. According to the method, all pins within the path are identified, and all timing edges defined by the pins within the path are identified. All pins within the path that are a leading pin of one of the time edge in the path are also identified. For each given pin within the path, a tabulation is made of a number of pins that are upstream from the given pin along a contiguous series of the timing edges in the path. A computational rank is assigned to the given pin based upon the tabulated number for the given pin. The timing edges are ordered for computation based upon the computational rank of the leading pin of each timing edge in the path, to produce an ordered list of timing edges. The timing delays of the timing edges of the path are computed according to the ordered list of timing edges.
摘要翻译：一种计算集成电路设计的路径的定时边缘的定时延迟的方法。根据该方法，识别路径内的所有引脚，并且识别由路径内的引脚限定的所有定时边缘。路径中的所有引脚都是路径中时间边缘之一的引导引脚。对于路径内的每个给定的引脚，列出了沿着路径中的连续的时序边缘序列从给定引脚上游的多个引脚。基于给定引脚的列表号码，给定引脚分配计算等级。定时边缘根据路径中每个时序边沿的引导引脚的计算等级进行排序，以产生定时边缘的有序列表。根据定时边缘的有序列表计算路径的定时边缘的定时延迟。

7. 发明授权

US06550044B1 Method in integrating clock tree synthesis and timing optimization for an integrated circuit design 有权
标题翻译：集成电路设计的时钟树合成和时序优化集成方法
公开(公告)号：US06550044B1
公开(公告)日：2003-04-15
申请号：US09885589
申请日：2001-06-19
申请人： Ivan Pavisic , Aiguo Lu , Andrej A. Zolotykh , Elyar E. Gasanov
发明人： Ivan Pavisic , Aiguo Lu , Andrej A. Zolotykh , Elyar E. Gasanov
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A method of synthesizing a clock tree for an integrated circuit design is disclosed that includes the steps of constructing an initial balanced clock tree for an integrated circuit design; calculating a clock arrival time for each clock driven cell in the initial clock tree; performing a timing analysis from the clock arrival time calculated for each clock driven cell; and performing a skew optimization concurrently with the timing analysis to correct timing violations discovered by the timing analysis.
摘要翻译：公开了一种合成用于集成电路设计的时钟树的方法，其包括以下步骤：为集成电路设计构建初始平衡时钟树; 计算初始时钟树中每个时钟驱动单元的时钟到达时间; 从针对每个时钟驱动单元计算的时钟到达时间执行时序分析; 并且与定时分析同时执行偏斜优化，以校正由定时分析发现的定时违规。

8. 发明申请

US20120278783A1 SIGNAL DELAY SKEW REDUCTION SYSTEM 失效
标题翻译：信号延迟减少系统
公开(公告)号：US20120278783A1
公开(公告)日：2012-11-01
申请号：US13544632
申请日：2012-07-09
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.
摘要翻译：提供了一种减少信号偏移的系统和方法。该方法包括接收具有组件之间的组件和连接的网表。每个连接具有至少一个信号线。识别多个网络组，每个网络组包括至少一些连接并且期望等效路由。对于每个网络组，所述方法包括系统地路由用于连接的组件之间的连接路径，每个连接路径在组件之一的输出和至少一个其他组件的输入之间延伸并且包括至少一个路径片段。对于网络组的至少一个连接，路由包括在与连接路径的路径片段中的至少一个相邻并且平行的路由信道中路由至少一个接地屏蔽线。

9. 发明授权

US07356785B2 Optimizing IC clock structures by minimizing clock uncertainty 失效
标题翻译：通过最小化时钟不确定性优化IC时钟结构
公开(公告)号：US07356785B2
公开(公告)日：2008-04-08
申请号：US11402146
申请日：2006-04-11
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G01R31/3016
摘要： A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.
摘要翻译：提供了一种用于优化具有由驱动器引脚限定的根和由驱动引脚限定的多个叶片的树形式的时钟网络的过程。该过程包括将第一缓冲区强制到多个叶片的重心，插入一组第二缓冲器，使得每个叶片被插入的缓冲器驱动而没有定时违反，并且将第一缓冲器移动到集合的重心的第二缓冲区。

10. 发明申请

US20060190901A1 Method of buffer insertion to achieve pin specific delays 有权
标题翻译：缓冲区插入方式来实现引脚特定的延迟
公开(公告)号：US20060190901A1
公开(公告)日：2006-08-24
申请号：US11041489
申请日：2005-01-24
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as output a revised integrated circuit design that includes the buffer sub-tree.
摘要翻译：一种用于集成电路设计中的树形网络的缓冲器插入方法包括以下步骤：（a）接收作为输入的包括树形网络的集成电路设计; （b）从单元库选择可用于集成电路设计的缓冲器类型，其导致预定导线长度的最小总延迟; （c）识别树网络中具有所需针特定目标延迟的候选叶节点; （d）在由候选叶节点到树网络的根节点的路径穿过的每个内部节点之间插入缓冲器，并且不是候选叶节点的每个叶节点; （e）从由候选叶节点到树网络的根节点的路径遍历的每个内部节点的上游内部节点在树形网络中创建缓冲器子树; 将通过从候选叶节点到树树网络的根节点的路径遍历的每个内部节点重新编入缓冲器子树中的新缓冲器; 和（g）产生包括缓冲器子树的经修订的集成电路设计的输出。

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