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    • 2. 发明授权
    • Memory interface architecture for maximizing access timing margin
    • 存储器接口架构,用于最大化访问时序裕量
    • US08230143B2
    • 2012-07-24
    • US11097903
    • 2005-04-01
    • Hui-Yin SetoCheng-Gang Kong
    • Hui-Yin SetoCheng-Gang Kong
    • G06F13/10
    • G06F13/1689
    • An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.
    • 一种包括控制电路,缓冲电路和存储器的装置。 控制电路可以被配置为响应于(i)以第一数据速率操作的一个或多个输入信号和(ii)以第二数据速率操作的输入时钟信号,呈现多对信号对。 每对中的第二信号包括以第二数据速率操作的时钟信号。 缓冲电路可以被配置为响应于每对信号产生缓冲信号。 每个缓冲信号以第二数据速率工作。 存储器可以被配置为响应于缓冲的信号以第二数据速率读取和写入数据。
    • 7. 发明授权
    • Programmable data strobe enable architecture for DDR memory applications
    • 可编程数据选通功能支持DDR存储器应用的架构
    • US07394707B2
    • 2008-07-01
    • US11166292
    • 2005-06-24
    • Hui-Yin SetoDerrick Sai-Tang Butt
    • Hui-Yin SetoDerrick Sai-Tang Butt
    • G11C7/00
    • G11C7/1066G11C7/1051G11C7/22
    • An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may include a plurality of first multiplexers and one or more second multiplexers configured to generate a first intermediate enable signal in response to (i) an input enable signal, (ii) a first clock signal operating at a first data rate and (iii) a plurality of first select signals. The plurality of first multiplexers each present an output to each of the one or more second multiplexers. The second circuit may be configured to generate a second intermediate enable signal in response to (i) the first intermediate enable signal, (ii) a second clock signal operating at a second data rate and (iii) a second select signal. The third circuit may be configured to generate a third intermediate enable signal in response to (i) the second intermediate enable signal, (ii) a control input signal and (iii) a third select signal. The third intermediate enable signal may be configured to control a read operation of a memory.
    • 一种包括第一电路,第二电路和第三电路的装置。 第一电路可以包括多个第一多路复用器和一个或多个第二多路复用器,其被配置为响应于(i)输入使能信号,(ii)以第一数据速率操作的第一时钟信号和( iii)多个第一选择信号。 多个第一多路复用器各自向一个或多个第二多路复用器中的每一个提供输出。 第二电路可以被配置为响应于(i)第一中间使能信号,(ii)以第二数据速率操作的第二时钟信号和(iii)第二选择信号来产生第二中间使能信号。 第三电路可以被配置为响应于(i)第二中间使能信号,(ii)控制输入信号和(iii)第三选择信号而产生第三中间​​使能信号。 第三中间使能信号可以被配置为控制存储器的读取操作。
    • 9. 发明申请
    • Memory interface architecture for maximizing access timing margin
    • 存储器接口架构,用于最大化访问时序裕量
    • US20060224847A1
    • 2006-10-05
    • US11097903
    • 2005-04-01
    • Hui-Yin SetoCheng-Gang Kong
    • Hui-Yin SetoCheng-Gang Kong
    • G06F13/00
    • G06F13/1689
    • An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.
    • 一种包括控制电路,缓冲电路和存储器的装置。 控制电路可以被配置为响应于(i)以第一数据速率操作的一个或多个输入信号和(ii)以第二数据速率操作的输入时钟信号,呈现多对信号对。 每对中的第二信号包括以第二数据速率操作的时钟信号。 缓冲电路可以被配置为响应于每对信号产生缓冲信号。 每个缓冲信号以第二数据速率工作。 存储器可以被配置为响应于缓冲的信号以第二数据速率读取和写入数据。