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1. 发明申请

US20110258587A1 SIGNAL DELAY SKEW REDUCTION SYSTEM 失效
标题翻译：信号延迟减少系统
公开(公告)号：US20110258587A1
公开(公告)日：2011-10-20
申请号：US13173855
申请日：2011-06-30
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，提供了一种用于减少信号延迟偏差的系统和方法。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括：接收在组件之间具有组件和连接路径的初始网表; 识别所述初始网表中的第一连接路径，其包括在所述初始网表中的第二连接路径中不存在等效路径片段的路径片段; 生成偏差校正网表，其中所述第二连接路径被重新路由以具有等同于所述第一连接路径的路径片段的路径片段; 并输出偏差校正的网表。

2. 发明申请

US20090187873A1 SIGNAL DELAY SKEW REDUCTION SYSTEM 有权
标题翻译：信号延迟减少系统
公开(公告)号：US20090187873A1
公开(公告)日：2009-07-23
申请号：US12015925
申请日：2008-01-17
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，公开了一种用于减小信号延迟偏差的系统。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括接收包括组件之间的组件和连接路径的初始网表。该方法还包括识别在初始网表中的第一连接路径中的一个或多个偏斜影响特征，其在初始网表中的第二连接路径中缺少对应的偏斜影响特征。该方法还包括生成偏差校正网表，其中第二连接路径包括与第一连接路径的相应的一个或多个相加的偏斜影响特征。该方法还包括输出经偏斜校正的网表。

3. 发明授权

US07546505B2 Built in self test transport controller architecture 失效
标题翻译：内置自检传输控制器架构
公开(公告)号：US07546505B2
公开(公告)日：2009-06-09
申请号：US11557513
申请日：2006-11-08
申请人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
发明人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C29/16 , G11C29/34 , G11C2029/0401 , G11C2029/1204 , G11C2029/2602
摘要： A built in self test circuit in a memory matrix. Memory cells within the matrix are disposed into columns. The circuit has only one memory test controller, adapted to initiate commands and receive results. Transport controllers are paired with the columns of memory cells. The controllers receive commands from the memory test controller, test memory cells within the column, receive test results, and provide the results to the memory test controller. The transport controllers operate in three modes. A production testing mode tests the memory cells in different columns, accumulating the results for a given column with the controller associated with the column. A production testing mode retrieves the results from the controllers. A diagnostic testing mode tests memory cells within one column, while retrieving results for the column.
摘要翻译：内存自检电路在内存矩阵中。矩阵内的存储单元被排列成列。该电路只有一个内存测试控制器，适用于启动命令并接收结果。传输控制器与存储单元的列配对。控制器从存储器测试控制器接收命令，测试列内的测试存储单元，接收测试结果，并将结果提供给存储器测试控制器。运输控制器以三种模式运行。生产测试模式测试不同列中的存储单元，使用与列相关联的控制器累积给定列的结果。生产测试模式从控制器检索结果。诊断测试模式测试一列内的存储单元，同时检索列的结果。

4. 发明授权

US07243324B2 Method of buffer insertion to achieve pin specific delays 有权
标题翻译：缓冲区插入方式来实现引脚特定的延迟
公开(公告)号：US07243324B2
公开(公告)日：2007-07-10
申请号：US11041489
申请日：2005-01-24
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as output a revised integrated circuit design that includes the buffer sub-tree.
摘要翻译：一种用于集成电路设计中的树形网络的缓冲器插入方法包括以下步骤：（a）接收作为输入的包括树形网络的集成电路设计; （b）从单元库选择可用于集成电路设计的缓冲器类型，其导致预定导线长度的最小总延迟; （c）识别树网络中具有所需针特定目标延迟的候选叶节点; （d）在由候选叶节点到树网络的根节点的路径穿过的每个内部节点之间插入缓冲器，并且不是候选叶节点的每个叶节点; （e）从由候选叶节点到树网络的根节点的路径遍历的每个内部节点的上游内部节点在树形网络中创建缓冲器子树; 将通过从候选叶节点到树树网络的根节点的路径遍历的每个内部节点重新编入缓冲器子树中的新缓冲器; 和（g）产生包括缓冲器子树的经修订的集成电路设计的输出。

5. 发明授权

US06901571B1 Timing-driven placement method utilizing novel interconnect delay model 失效
标题翻译：利用新型互连延迟模型的定时驱动放置方法
公开(公告)号：US06901571B1
公开(公告)日：2005-05-31
申请号：US09010396
申请日：1998-01-21
申请人： Dusan Petranovic , Ranko Scepanovic , Ivan Pavisic
发明人： Dusan Petranovic , Ranko Scepanovic , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for optimal placement of cells on a surface of an integrated circuit, comprising the steps of comparing a placement of cells to predetermined cost criteria and moving cells to alternate locations on the surface if necessary to satisfy the cost criteria. The cost criteria include a timing criterion based upon interconnect delay, where interconnect delay is modeled as a RC tree expressed as a function of pin-to-pin distance. The method accounts for driver to sink interconnect delay at the placement level, a novel aspect resulting from use of the RC tree model, which maximally utilizes available net information to produce an optimal timing estimate. Preferred versions utilize a RC tree interconnect delay model that is consistent with timing models used at design levels above placement, such as synthesis, and below placement, such as routing. Additionally, preferred versions can utilize either a constructive placement or iterative improvement placement method.
摘要翻译：一种用于在集成电路的表面上最佳地放置单元的方法，包括以下步骤：如果需要满足成本标准，将单元的布局与预定成本标准进行比较并将单元移动到表面上的替代位置。成本标准包括基于互连延迟的定时标准，其中互连延迟被建模为作为针对针距离的函数的RC树。该方法考虑了驱动程序以在布局级别中接收互连延迟，这是由使用RC树模型产生的新颖的方面，其最大限度地利用可用的网络信息来产生最佳的时序估计。首选版本使用RC树互连延迟模型，其与在布局之上的设计级别（例如合成）以及在布局之下（例如路由）使用的定时模型一致。另外，优选版本可以利用建设性位置或迭代改进放置方法。

6. 发明授权

US06757877B2 System and method for identifying and eliminating bottlenecks in integrated circuit designs 失效
标题翻译：识别和消除集成电路设计瓶颈的系统和方法
公开(公告)号：US06757877B2
公开(公告)日：2004-06-29
申请号：US10083411
申请日：2002-02-27
申请人： Robert Stenberg , Ivan Pavisic
发明人： Robert Stenberg , Ivan Pavisic
IPC分类号： G06F1750
CPC分类号： G06F17/5031 , G06F17/5068
摘要： A method of integrated circuit design and a circuit design tool. Critical paths are identified in an integrated circuit design. Identified edges are weighted. Edges are assigned a higher weight responsive to the number of critical paths in which they are included. A net criticality is assigned to each weighted edge based upon the edge's weight. Cells are re-placed and wired according to net criticality.
摘要翻译：一种集成电路设计方法和电路设计工具。集成电路设计中确定了关键路径。识别的边被加权。响应于包括它们的关键路径的数量，边缘被赋予更高的权重。基于边缘权重，将每个加权边缘分配净关键度。细胞根据净临界值重新放置和布线。

7. 发明授权

US06701493B2 Floor plan tester for integrated circuit design 失效
标题翻译：集成电路设计平面图测试仪
公开(公告)号：US06701493B2
公开(公告)日：2004-03-02
申请号：US10109113
申请日：2002-03-27
申请人： Elyar E. Gasanov , Andrej A. Zolotykh , Ivan Pavisic , Aiguo Lu
发明人： Elyar E. Gasanov , Andrej A. Zolotykh , Ivan Pavisic , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method of testing a floor plan for an integrated circuit prior to resynthesis includes attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has an unreachable pin; and if the least-penalty path is constructed, then attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has a bottleneck.
摘要翻译：在再合成之前测试集成电路的平面图的方法包括尝试构造在平面图中连接每个长距离销对的销的最小惩罚路径，以确定平面图是否具有不可达的销; 并且如果构造最小惩罚路径，则尝试构建在平面图中连接每个长距离销对的销的最小惩罚路径，以确定平面图是否具有瓶颈。

8. 发明授权

US06629304B1 Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells 有权
标题翻译：电池放置在集成电路芯片中，以去除单元重叠，行溢出和双高度单元的最佳放置
公开(公告)号：US06629304B1
公开(公告)日：2003-09-30
申请号：US09955698
申请日：2001-09-19
申请人： Elyar E. Gasanov , Andrej A. Zolotykh , Aiguo Lu , Ivan Pavisic
发明人： Elyar E. Gasanov , Andrej A. Zolotykh , Aiguo Lu , Ivan Pavisic
IPC分类号： G06F945
CPC分类号： G06F17/5072
摘要： Cell overlap is removed from rows during a cell placement procedure for an integrated circuit chip. The rows are partitioned into subrows so that cells in each subrow have a common characteristic vector. Cell overflow is removed from each of the subrows by moving a cell of an overflowed row or exchanging two cells, at least one of which is in the overflowed subrow. The half-cells of the dual height cells are moved to cell positions in a suitable pair of rows based on a calculated movement penalty. The movement is accomplished to align the half-cells and minimize the penalty. In preferred embodiments, the process is carried out by a computer under control of a computer program.
摘要翻译：在集成电路芯片的单元放置过程期间，从行中移除单元格重叠。行被划分为子行，使得每个子行中的单元具有公共特征向量。通过移动溢出的行的单元或交换两个单元，其中至少一个在溢出的子行中，从每个子行移除单元溢出。基于所计算的运动损失，双高度单元的半单元以合适的行对移动到单元位置。完成运动以对准半细胞并最小化处罚。在优选实施例中，该过程由计算机在计算机程序的控制下执行。

9. 发明授权

US06546541B1 Placement-based integrated circuit re-synthesis tool using estimated maximum interconnect capacitances 有权
标题翻译：基于放置的集成电路重合成工具，使用估计的最大互连电容
公开(公告)号：US06546541B1
公开(公告)日：2003-04-08
申请号：US09789108
申请日：2001-02-20
申请人： Dusan Petranovic , Ivan Pavisic , Aiguo Lu
发明人： Dusan Petranovic , Ivan Pavisic , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/505
摘要： A method and apparatus are provided for generating constraints for an integrated circuit logic re-synthesis algorithm. The method and apparatus receive a netlist of interconnected logic elements, which includes a plurality of nets, wherein each of the nets is coupled between a respective net driver logic element and at least one driven logic element. The method and apparatus also receive a maximum allowable input ramp time specification for the logic elements and an output ramp time specification for the net driver logic elements. A maximum interconnect capacitance constraint is then generated for each of the net driver logic elements based on the output ramp time specification for that net driver logic element and the maximum allowable input ramp time specification.
摘要翻译：提供了一种用于为集成电路逻辑重新合成算法产生约束的方法和装置。所述方法和装置接收互连的逻辑元件的网表，其包括多个网络，其中每个网络耦合在相应的网络驱动器逻辑元件和至少一个驱动逻辑元件之间。该方法和装置还接收用于逻辑元件的最大允许输入斜坡时间规范和用于网络驱动器逻辑元件的输出斜坡时间规范。然后，基于该网络驱动器逻辑元件的输出斜坡时间规范和最大允许输入斜坡时间规范，为每个网络驱动器逻辑元件生成最大互连电容约束。

10. 发明授权

US6038385A Physical design automation system and process for designing integrated circuit chip using "chessboard" and "jiggle" optimization 失效
标题翻译：物理设计自动化系统和使用“棋盘”和“抖动”优化设计集成电路芯片的过程
公开(公告)号：US6038385A
公开(公告)日：2000-03-14
申请号：US609397
申请日：1996-03-01
申请人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , James S. Koford , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. A placement improvement operation such as simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge. The jiggles enable cells to move to their optimal positions from their initial region to any other region on the chip. The regions can have rectangular, triangular or hexagonal shapes.
摘要翻译：集成电路芯片的单元布局分为两个“棋盘”图案或“跳棋”。每个图案类似于棋盘，其由不同类型或“颜色”的交替区域组成，使得给定颜色的区域不具有与相同颜色的另一区域相同的边缘。跳块相对于彼此偏移，使得一个颤动的区域部分地与另一个摇摆的至少两个区域重叠。针对每个抖动的每个颜色顺序地执行诸如模拟退火的放置改善操作。在每个操作期间，多个并行处理器使用整个芯片的先前副本同时在该区域上操作，一个处理器被分配给一个或多个区域。在每个操作结束时，更新芯片的副本。棋盘图案消除由具有共同边缘的相邻区域产生的非生产性细胞移动。这些跳跃使得电池从它们的初始区域移动到其最佳位置到芯片上的任何其它区域。这些区域可以具有矩形，三角形或六边形形状。

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