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    • 2. 发明授权
    • System and method for dynamically switching between low and high frequency reference clock to PLL and minimizing PLL output frequency changes
    • 用于在低频和高频参考时钟之间动态切换到PLL并最小化PLL输出频率变化的系统和方法
    • US08125253B2
    • 2012-02-28
    • US12610438
    • 2009-11-02
    • Stanley GoldmanSrinath Ramaswamy
    • Stanley GoldmanSrinath Ramaswamy
    • H03L7/06
    • H03L7/193H03L7/093
    • A circuit is provided for use with a clock having an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion receives a reference signal and outputs a divided reference signal. The feedback divider portion receives an output signal from the circuit and outputs a divided feedback signal. The phase detector portion outputs a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion outputs a tuning signal based on the phase detector signal. The voltage controlled oscillator portion output the outputs a signal based on the tuning signal. The phase detector portion changes the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal.
    • 提供了一种与具有输入分频器部分,反馈分频器部分,相位检测器部分,环路补偿滤波器部分和压控振荡器部分的时钟一起使用的电路。 输入分频器部分接收参考信号并输出​​分频的参考信号。 反馈分配器部分接收来自电路的输出信号并输出​​分频的反馈信号。 相位检测器部分基于划分的参考信号和分离的反馈信号输出相位检测器信号。 环路补偿滤波器部分基于相位检测器信号输出调谐信号。 压控振荡器部分输出基于调谐信号的信号。 相位检测器部分基于接收控制信号的输入分频器部分和接收控制信号的反馈分频器部分来改变相位检测器信号。
    • 3. 发明申请
    • High frequency transmission gate buffer
    • 高频传输门缓冲器
    • US20070085577A1
    • 2007-04-19
    • US11253486
    • 2005-10-18
    • Stanley Goldman
    • Stanley Goldman
    • H03B1/00
    • H03K5/151H03K19/018521H03K19/09429
    • An apparatus for providing a signal to a transmission medium. A first switching stage is connected in series between a source voltage and a transmission medium, and a second switching stage connected in series between the transmission medium and a reference line. The first and second switching stages each comprise at least one p channel transistor in parallel with at least one n channel transistor. The first and second switching stages are preferably configured to substantially symmetrically drive the transmission medium at a frequency of at least 4 gigahertz (GHz). The stages are further preferably characterized as variable resistance stages with lower resistance at the rails as compared to the midpoint of the input signal. Additional sets of stages can be provided to facilitate multiple outputs.
    • 一种用于向传输介质提供信号的装置。 第一开关级串联连接在源电压和传输介质之间,第二开关级串联连接在传输介质和参考线之间。 第一和第二开关级各自包括与至少一个n沟道晶体管并联的至少一个p沟道晶体管。 第一和第二开关级优选地构造成以至少4千兆赫(GHz)的频率基本上对称地驱动传输介质。 这些级进一步优选地被表征为与输入信号的中点相比在轨道处具有较低电阻的可变电阻级。 可以提供额外的级级,以便于多个输出。
    • 4. 发明申请
    • SYSTEM AND METHOD FOR DYNAMICALLY SWITCHING BETWEEN LOW AND HIGH FREQUENCY REFERENCE CLOCK TO PLL AND MINIMIZING PLL OUTPUT FREQUENCY CHANGES
    • 低频和高频参考时钟之间的动态切换到PLL和最小化PLL输出频率变化的系统和方法
    • US20110102030A1
    • 2011-05-05
    • US12610438
    • 2009-11-02
    • Stanley GoldmanSrinath Ramaswamy
    • Stanley GoldmanSrinath Ramaswamy
    • H03L7/06
    • H03L7/193H03L7/093
    • A circuit is provided for use with a clock signal having a plurality of clock pulses, each clock pulse having a rising edge and a falling edge. The circuit is operable to receive a reference signal and to output an output signal. The circuit includes an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion is arranged to receive the reference signal and is operable to output a divided reference signal. The feedback divider portion is arranged to receive the output signal and is operable to output a divided feedback signal. The phase detector portion is operable to output a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion is operable to output a tuning signal based on the phase detector signal. The voltage controlled oscillator portion is operable to output the output signal based on the tuning signal. The phase detector portion is further operable to change the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal, and further based on the control signal and a rising edge of a clock pulse.
    • 提供电路用于具有多个时钟脉冲的时钟信号,每个时钟脉冲具有上升沿和下降沿。 电路可操作以接收参考信号并输出​​输出信号。 电路包括输入分频器部分,反馈分频器部分,相位检测器部分,环路补偿滤波器部分和压控振荡器部分。 输入分频器部分被布置成接收参考信号并且可操作以输出分频的参考信号。 反馈分配器部分被布置成接收输出信号并且可操作以输出分离的反馈信号。 相位检测器部分可操作以基于划分的参考信号和分频反馈信号输出相位检测器信号。 环路补偿滤波器部分可操作以基于相位检测器信号输出调谐信号。 压控振荡器部分可操作以基于调谐信号输出输出信号。 相位检测器部分还可操作以基于接收控制信号的输入分频器部分和接收控制信号的反馈分频器部分,并且还基于控制信号和时钟脉冲的上升沿来改变相位检测器信号。
    • 7. 发明申请
    • Hybrid control of phase locked loops
    • 锁相环的混合控制
    • US20060009184A1
    • 2006-01-12
    • US10885909
    • 2004-07-07
    • Stanley Goldman
    • Stanley Goldman
    • H04B17/00
    • H03L7/093H03L7/0995H03L7/18H03L2207/06
    • A hybrid digital and analog phase locked loop. A voltage controlled oscillator is provided, having a fine tune input, a coarse tune input and an output. A frequency divider has an input connected to receive a signal provided by the output of the voltage controlled oscillator, and has an output for providing a signal having a frequency that is divided with respect to a signal provided to its input. A phase detector is connected to receive a reference input signal having a reference frequency at a first input thereof and is connected to receive the signal provided by the output of the frequency divider. The phase detector has an output for providing a phase error signal. An analog is circuit configured as a proportional filter and is connected to receive the phase error signal and to provide a fine tune signal at the fine tune input of the voltage controlled oscillator. A digital integrator is connected to receive the phase error signal and to provide a coarse tune signal at the coarse tune input of the voltage controlled oscillator.
    • 混合数字和模拟锁相环。 提供压控振荡器,具有微调输入,粗调输入和输出。 分频器具有连接的输入端以接收由压控振荡器的输出提供的信号,并且具有用于提供具有相对于提供给其输入的信号被分频的频率的信号的输出。 相位检测器被连接以在其第一输入处接收具有参考频率的参考输入信号,并被连接以接收由分频器的输出提供的信号。 相位检测器具有用于提供相位误差信号的输出。 模拟电路被配置为比例滤波器,并被连接以接收相位误差信号并且在压控振荡器的微调输入处提供微调信号。 连接数字积分器以接收相位误差信号,并在压控振荡器的粗调输入端提供粗调信号。