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1. 发明申请

US20110042006A1 E-CHUCK WITH AUTOMATED CLAMPED FORCE ADJUSTMENT AND CALIBRATION 有权
标题翻译：具有自动钳位力调整和校准的电动自行车
公开(公告)号：US20110042006A1
公开(公告)日：2011-02-24
申请号：US12938610
申请日：2010-11-03
申请人： Jo Fei Wang , Sunny Wu , Jong-I Mou
发明人： Jo Fei Wang , Sunny Wu , Jong-I Mou
IPC分类号： H01L21/46 , G06F19/00 , H01L21/465
CPC分类号： H01L21/6831 , H01L22/20 , H01L2924/0002 , Y10S438/909 , H01L2924/00
摘要： The present disclosure describes a semiconductor manufacturing apparatus. The apparatus includes a processing chamber designed to perform a process to a wafer; an electrostatic chuck (E-chuck) configured in the processing chamber and designed to secure the wafer, wherein the E-chuck includes an electrode and a dielectric feature formed on the electrode; a tuning structure designed to hold the E-chuck to the processing chamber by clamping forces, wherein the tuning structure is operable to dynamically adjust the clamping forces; a sensor integrated with the E-chuck and sensitive to the clamping forces; and a process control module for controlling the tuning structure to adjust the clamping forces based on pre-measurement data from the wafer and sensor data from the sensor.
摘要翻译：本公开描述了一种半导体制造装置。该设备包括设计成对晶片执行处理的处理室; 配置在所述处理室中并设计成固定所述晶片的静电卡盘（E卡盘），其中所述E卡盘包括形成在所述电极上的电极和电介质特征; 调谐结构，其被设计成通过夹紧力将所述E卡盘保持在所述处理室中，其中所述调谐结构可操作以动态地调节所述夹紧力; 与E型卡盘集成并对夹紧力敏感的传感器; 以及过程控制模块，用于基于来自晶片的预测量数据和来自传感器的传感器数据来控制调谐结构以调整夹紧力。

2. 发明授权

US08219341B2 System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) with routing model 有权
标题翻译：使用路由模型实现晶片验收测试（“WAT”）高级过程控制（“APC”）的系统和方法
公开(公告)号：US08219341B2
公开(公告)日：2012-07-10
申请号：US12411680
申请日：2009-03-26
申请人： Andy Tsen , Sunny Wu , Wang Jo Fei , Jong-I Mou
发明人： Andy Tsen , Sunny Wu , Wang Jo Fei , Jong-I Mou
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/14
摘要： System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing an inter-metal (“IM”) WAT on a plurality of processed wafer lots; selecting a subset of the plurality of wafer lots using a lot sampling process; and selecting a sample wafer group using the wafer lot subset, wherein IM WAT is performed on wafers of the sample wafer group to obtain IM WAT data therefore. The method further comprises estimating final WAT data for all wafers in the processed wafer lots from IM WAT data obtained for the sample wafer group and providing the estimated final WAT data to a WAT APC process for controlling processes.
摘要翻译：描述了实现晶片验收测试（“WAT”）高级过程控制（“APC”）的系统和方法。在一个实施例中，该方法包括在多个经处理的晶片批次上执行金属间（“IM”）WAT; 使用批次采样处理来选择所述多个晶片批次的子集; 以及使用晶片批次子集选择样品晶片组，因此在样品晶片组的晶片上执行IM WAT以获得IM WAT数据。该方法还包括从针对样品晶片组获得的IM WAT数据估计经处理的晶片批次中的所有晶片的最终WAT数据，并将估计的最终WAT数据提供给用于控制过程的WAT APC过程。

3. 发明授权

US08205173B2 Physical failure analysis guiding methods 有权
标题翻译：物理故障分析指导方法
公开(公告)号：US08205173B2
公开(公告)日：2012-06-19
申请号：US12818003
申请日：2010-06-17
申请人： Sunny Wu , Yen-Di Tsen , Monghsung Chuang , Fu-Min Huang , Jo Fei Wang , Jong-I Mou
发明人： Sunny Wu , Yen-Di Tsen , Monghsung Chuang , Fu-Min Huang , Jo Fei Wang , Jong-I Mou
IPC分类号： G06F17/50 , G06F19/00 , G06F11/00 , G01R31/00
CPC分类号： G01R31/2894
摘要： A method includes providing a plurality of failure dies, and performing a chip probing on the plurality of failure dies to generate a data log comprising electrical characteristics of the plurality of failure dies. An automatic net tracing is performed to trace failure candidate nodes in the failure dies. A failure layer analysis is performed on results obtained from the automatic net tracing. Physical failure analysis (PFA) samples are selected from the plurality of failure dies using results obtained in the step of performing the failure layer analysis.
摘要翻译：一种方法包括提供多个故障管芯，并对多个故障管芯进行芯片探测以产生包括多个故障管芯的电气特性的数据记录。执行自动网络跟踪以跟踪故障模块中的故障候选节点。对从自动网络跟踪获得的结果执行故障层分析。使用在执行故障层分析的步骤中获得的结果从多个故障模具中选择物理故障分析（PFA）样本。

4. 发明授权

US08108060B2 System and method for implementing a wafer acceptance test (“WAT”) advanced process control (“APC”) with novel sampling policy and architecture 有权
标题翻译：采用新颖的采样策略和架构实现晶片验收测试（“WAT”）高级过程控制（“APC”）的系统和方法
公开(公告)号：US08108060B2
公开(公告)日：2012-01-31
申请号：US12465064
申请日：2009-05-13
申请人： Andy Tsen , Jo Fei Wang , Po-Feng Tsai , Ming-Yu Fan , Jill Wang , Jong-I Mou , Sunny Wu
发明人： Andy Tsen , Jo Fei Wang , Po-Feng Tsai , Ming-Yu Fan , Jill Wang , Jong-I Mou , Sunny Wu
IPC分类号： G06F19/00 , G06F17/18 , G06F11/30 , G01N37/00
CPC分类号： G05B13/048 , G05B19/41875 , Y02P90/22 , Y02P90/86
摘要： System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing a key process on a sample number of wafers of a lot of wafers; performing a key inline measurement related to the key process to produce metrology data for the wafers; predicting WAT data from the metrology data using an inline-to-WAT model; and using the predicted WAT data to tune a WAT APC process for controlling a tuning process or a process APC process.
摘要翻译：描述了实现晶片验收测试（“WAT”）高级过程控制（“APC”）的系统和方法。在一个实施例中，该方法包括对大量晶片的晶片的样本数进行密钥处理; 执行关键过程的关键在线测量以产生晶片的测量数据; 使用直线到WAT模型预测来自计量数据的WAT数据; 并且使用预测的WAT数据来调整用于控制调谐过程或过程APC过程的WAT APC过程。

5. 发明授权

US08082055B2 Method for a bin ratio forecast at new tape out stage 有权
标题翻译：新磁带出站时的比例预测方法
公开(公告)号：US08082055B2
公开(公告)日：2011-12-20
申请号：US12499345
申请日：2009-07-08
申请人： Chun-Hsien Lin , Andy Tsen , Jui-Long Chen , Sunny Wu , Jong-I Mou , Chia-Hung Huang
发明人： Chun-Hsien Lin , Andy Tsen , Jui-Long Chen , Sunny Wu , Jong-I Mou , Chia-Hung Huang
IPC分类号： G06F19/00
CPC分类号： G06Q10/06 , G06Q30/0202
摘要： A method for providing a bin ratio forecast at an early stage of integrated circuit device manufacturing processes is disclosed. The method comprises collecting historical data from one or more processed wafer lots; collect measurement data from one or more skew wafer lots; generating an estimated baseline distribution from the collected historical data and collected measurement data; generating an estimated performance distribution based on one or more specified parameters and the generated estimated baseline distribution; determining a bin ratio forecast by applying a bin definition and a yield degradation factor estimation to the generated estimated performance distribution; determining one or more production targets based on the bin ratio forecast; and processing one or more wafers based on the one or more determined production targets.
摘要翻译：公开了一种用于在集成电路器件制造工艺的早期阶段提供容量比预测的方法。该方法包括从一个或多个处理的晶片批次收集历史数据; 从一个或多个偏斜晶片批量收集测量数据; 从收集的历史数据和收集的测量数据生成估计的基线分布; 基于一个或多个指定参数和所生成的估计基线分布产生估计的性能分布; 通过对所生成的估计性能分布应用仓定义和产量退化因子估计来确定仓比预测; 根据仓比预测确定一个或多个生产目标; 以及基于所述一个或多个确定的生产目标来处理一个或多个晶圆。

6. 发明授权

US08041451B2 Method for bin-based control 有权
标题翻译：基于bin的控制方法
公开(公告)号：US08041451B2
公开(公告)日：2011-10-18
申请号：US12427154
申请日：2009-04-21
申请人： Sunny Wu , Chih-Sheng Shih , Andy Tsen , Jo Fei Wang , Jong-I Mou , Hsin Kuan
发明人： Sunny Wu , Chih-Sheng Shih , Andy Tsen , Jo Fei Wang , Jong-I Mou , Hsin Kuan
IPC分类号： G06F7/00 , G06F19/00 , G06F17/00 , G06Q10/00
CPC分类号： G05B19/41865 , G05B2219/32097 , G05B2219/32256 , G05B2219/32324 , G05B2219/45031 , G06Q10/087 , Y02P90/14 , Y02P90/20
摘要： A method for providing bin-based control when manufacturing integrated circuit devices is disclosed. The method comprises performing a plurality of processes on a plurality of wafer lots; determining a required bin quantity, an actual bin quantity, and a projected bin quantity; comparing the determined required bin quantity with the determined actual bin quantity and determined projected bin quantity; and modifying at least one of the plurality of processes on the plurality of wafer lots if the determined actual bin quantity and determined projected bin quantity fail to satisfy the determined required bin quantity.
摘要翻译：公开了一种在制造集成电路器件时提供基于bin的控制的方法。该方法包括在多个晶片批次上执行多个处理; 确定所需的仓数量，实际箱数量和投影箱数量; 将确定的所需仓量与确定的实际箱数量和确定的预计仓量进行比较; 以及如果所确定的实际仓量和确定的投影箱数量不能满足所确定的所需仓量，则修改多个晶片批次上的多个处理中的至少一个。

7. 发明申请

US20100268367A1 METHOD FOR BIN-BASED CONTROL 有权
标题翻译：基于BIN的控制方法
公开(公告)号：US20100268367A1
公开(公告)日：2010-10-21
申请号：US12427154
申请日：2009-04-21
申请人： Sunny Wu , Chih-Sheng Shih , Andy Tsen , Jo Fei Wang , Jong-I Mou , Hsin Kuan
发明人： Sunny Wu , Chih-Sheng Shih , Andy Tsen , Jo Fei Wang , Jong-I Mou , Hsin Kuan
IPC分类号： G06F17/00
CPC分类号： G05B19/41865 , G05B2219/32097 , G05B2219/32256 , G05B2219/32324 , G05B2219/45031 , G06Q10/087 , Y02P90/14 , Y02P90/20
摘要： A method for providing bin-based control when manufacturing integrated circuit devices is disclosed. The method comprises performing a plurality of processes on a plurality of wafer lots; determining a required bin quantity, an actual bin quantity, and a projected bin quantity; comparing the determined required bin quantity with the determined actual bin quantity and determined projected bin quantity; and modifying at least one of the plurality of processes on the plurality of wafer lots if the determined actual bin quantity and determined projected bin quantity fail to satisfy the determined required bin quantity.
摘要翻译：公开了一种在制造集成电路器件时提供基于bin的控制的方法。该方法包括在多个晶片批次上执行多个处理; 确定所需的仓数量，实际箱数量和投影箱数量; 将确定的所需仓量与确定的实际箱数量和确定的预计仓量进行比较; 以及如果所确定的实际仓量和确定的投影箱数量不能满足所确定的所需仓量，则修改多个晶片批次上的多个处理中的至少一个。

8. 发明申请

US20100250172A1 SYSTEM AND METHOD FOR IMPLEMENTING WAFER ACCEPTANCE TEST ("WAT") ADVANCED PROCESS CONTROL ("APC") WITH ROUTING MODEL 有权
标题翻译：使用路由模型实现波形接收测试（“WAT”）高级过程控制（“APC”）的系统和方法
公开(公告)号：US20100250172A1
公开(公告)日：2010-09-30
申请号：US12411680
申请日：2009-03-26
申请人： Andy Tsen , Sunny Wu , Wang Jo Fei , Jong-I Mou
发明人： Andy Tsen , Sunny Wu , Wang Jo Fei , Jong-I Mou
IPC分类号： G06F19/00 , G01N37/00
CPC分类号： H01L22/20 , H01L22/14
摘要： System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing an inter-metal (“IM”) WAT on a plurality of processed wafer lots; selecting a subset of the plurality of wafer lots using a lot sampling process; and selecting a sample wafer group using the wafer lot subset, wherein IM WAT is performed on wafers of the sample wafer group to obtain IM WAT data therefore. The method further comprises estimating final WAT data for all wafers in the processed wafer lots from IM WAT data obtained for the sample wafer group and providing the estimated final WAT data to a WAT APC process for controlling processes.
摘要翻译：描述了实现晶片验收测试（“WAT”）高级过程控制（“APC”）的系统和方法。在一个实施例中，该方法包括在多个经处理的晶片批次上执行金属间（“IM”）WAT; 使用批次采样处理来选择所述多个晶片批次的子集; 以及使用晶片批次子集选择样品晶片组，因此在样品晶片组的晶片上执行IM WAT以获得IM WAT数据。该方法还包括从针对样品晶片组获得的IM WAT数据估计经处理的晶片批次中的所有晶片的最终WAT数据，并将估计的最终WAT数据提供给用于控制过程的WAT APC过程。

9. 发明授权

US07083495B2 Advanced process control approach for Cu interconnect wiring sheet resistance control 失效
标题翻译： Cu互连布线电阻控制的先进工艺控制方法
公开(公告)号：US07083495B2
公开(公告)日：2006-08-01
申请号：US10723236
申请日：2003-11-26
申请人： Chun Hsien Lin , Ai-Sen Liu , Sunny Wu , Yu-Liang Lin , Henry Lo , Mei-Sheng Zhou
发明人： Chun Hsien Lin , Ai-Sen Liu , Sunny Wu , Yu-Liang Lin , Henry Lo , Mei-Sheng Zhou
IPC分类号： B24B49/00 , B24B1/00
CPC分类号： B24B51/00 , B24B37/042 , G05B13/024 , H01L21/31053 , H01L21/3212
摘要： A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3σ variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.
摘要翻译：描述了用于控制氧化物（Cu或TaN）抛光步骤的基于晶圆的APC方法，并且组合了用于补偿进入晶片变化的前馈模型与补偿CMP变化的馈送反向模型。该方法面向最小化Rs 3sigma变化。输入Rs目标值，其中来自先前工艺的测量数据影响铜层的宽度和厚度。确定第一晶片的铜厚度目标和抛光时间。第一晶片的CMP后测量数据被用于利用干扰因子修改抛光速率，并且为随后的晶片计算更新的抛光时间。每个晶片的CMP配方用测量数据和后CMP测量进行调整。 APC方法成功地控制了90nm技术节点的铜Rs变化，并且与铜图案密度无关。

10. 发明授权

US5016849A Swivel mechanism for a monitor of a laptop computer 失效
标题翻译：笔记本电脑显示器的旋转机构
公开(公告)号：US5016849A
公开(公告)日：1991-05-21
申请号：US437594
申请日：1989-11-17
申请人： Sunny Wu
发明人： Sunny Wu
IPC分类号： E05D3/06 , E05D11/08 , F16M11/12
CPC分类号： F16M11/10 , F16M11/2014 , F16M13/005 , G06F1/1616 , G06F1/1681 , E05D11/082 , E05D3/12 , E05Y2900/606 , F16M2200/041 , F16M2200/044 , Y10S248/923
摘要： This invention relates a swivel mechanism for a monitor of a laptop computer and in particular to one utilizing four tightly fitted axles in the same direction to be its horizontal axis and a tightly fitted upright axle to be its vertical axis so as to enable the monitor to rotate with respect to the horizontal and the vertical axes when pushed by the user thereby widening the visible range and thus, increasing the working efficiency and the feasibility as well.
摘要翻译：本发明涉及一种用于膝上型计算机的监视器的旋转机构，特别涉及一种以相同方向的四个紧密配合的轴作为其水平轴线的方式，以及紧密配合的直立轴作为其垂直轴线，以使监视器能够相对于水平轴和垂直轴旋转，从而使用户可视范围变宽，从而提高工作效率和可行性。

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