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1. 发明授权

US09026239B2 APC model extension using existing APC models 有权
标题翻译： APC型号扩展使用现有的APC型号
公开(公告)号：US09026239B2
公开(公告)日：2015-05-05
申请号：US12793307
申请日：2010-06-03
申请人： Po-Feng Tsai , Yen-Di Tsen , Jo Fei Wang , Jong-I Mou
发明人： Po-Feng Tsai , Yen-Di Tsen , Jo Fei Wang , Jong-I Mou
IPC分类号： G06F19/00 , G05B11/01 , G05B17/02 , G05B15/00 , H01L21/66
CPC分类号： G05B17/02 , H01L22/20
摘要： A method of extending advanced process control (APC) models includes constructing an APC model table including APC model parameters of a plurality of products and a plurality of work stations. The APC model table includes empty cells and cells filled with existing APC model parameters. Average APC model parameters of the existing APC model parameters are calculated, and filled into the empty cells as initial values. An iterative calculation is performed to update the empty cells with updated values.
摘要翻译：扩展先进过程控制（APC）模型的方法包括构建包括多个产品的APC模型参数和多个工作站的APC模型表。 APC模型表包括空单元格和填充有现有APC模型参数的单元格。计算现有APC模型参数的平均APC模型参数，并作为初始值填充到空单元格中。执行迭代计算以更新值更新空单元格。

2. 发明授权

US08793638B2 Method of optimizing design for manufacturing (DFM) 有权
标题翻译：优化制造设计（DFM）的方法
公开(公告)号：US08793638B2
公开(公告)日：2014-07-29
申请号：US13559081
申请日：2012-07-26
申请人： Keuing Hui , Yen-Wei Cheng , Yen-Di Tsen , Jong-I Mou , Chin-Hsiang Lin
发明人： Keuing Hui , Yen-Wei Cheng , Yen-Di Tsen , Jong-I Mou , Chin-Hsiang Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters.
摘要翻译：本公开描述了优化用于制造（DFM）仿真的设计的方法。该方法包括接收具有特征的集成电路（IC）设计数据，接收具有参数或多个参数的处理数据，执行DFM仿真和优化DFM仿真。执行DFM模拟包括使用IC设计数据和过程数据生成模拟输出数据。优化DFM模拟包括通过DFM仿真生成参数或多个参数的性能指标。优化DFM模拟包括调整外循环，中间循环和内循环的参数或多个参数。优化DFM模拟还包括在参数或多个参数的范围内定位参数或多个参数的性能指标的最低点。

3. 发明授权

US08406904B2 Two-dimensional multi-products multi-tools advanced process control 有权
标题翻译：二维多产品多工具高级过程控制
公开(公告)号：US08406904B2
公开(公告)日：2013-03-26
申请号：US13033413
申请日：2011-02-23
申请人： Chih-Wei Hsu , Yen-Di Tsen , Jong-I Mou
发明人： Chih-Wei Hsu , Yen-Di Tsen , Jong-I Mou
IPC分类号： G05B13/02 , G06F19/00
CPC分类号： G05B19/41865 , G05B2219/32135 , G05B2219/32267 , G05B2219/45031 , Y02P90/20 , Y02P90/265
摘要： The present disclosure provides a method. The method includes gathering advanced process control (APC) data from a subset of available wafers and a subset of available processing chambers. The method includes establishing a matrix that contains a plurality of cells. The cells each correspond to one of the available wafers and one of the available processing chambers. The matrix is partially filled by populating cells for which the APC data has been gathered. The method includes determining a plurality of chamber-coverage-rate (CCR) parameters associated with the matrix. The method includes optimizing the CCR parameters through an iteration process to obtain optimized CCR parameters. The method includes predicting an APC data value for a designated cell of the matrix based on the optimized CCR parameters. The designated cell is an empty cell before the predicting and is populated by the predicting.
摘要翻译：本公开提供了一种方法。该方法包括从可用晶片的子集和可用处理室的子集中收集先进的过程控制（APC）数据。该方法包括建立包含多个单元的矩阵。每个单元对应于可用晶片之一和可用处理室之一。通过填充已经收集了APC数据的单元格来部分填充矩阵。该方法包括确定与矩阵相关联的多个腔室覆盖率（CCR）参数。该方法包括通过迭代过程优化CCR参数以获得优化的CCR参数。该方法包括基于优化的CCR参数预测矩阵的指定小区的APC数据值。指定的单元格是在预测之前的空单元格，并由预测填充。

4. 发明授权

US08288063B2 Defense system in advanced process control 有权
标题翻译：国防系统在先进的过程控制中
公开(公告)号：US08288063B2
公开(公告)日：2012-10-16
申请号：US12844507
申请日：2010-07-27
申请人： Shin-Rung Lu , Chih Ming Hong , Yen-Di Tsen
发明人： Shin-Rung Lu , Chih Ming Hong , Yen-Di Tsen
IPC分类号： G03F9/00
CPC分类号： G03F7/70633 , G03F7/70525
摘要： A method includes performing a lithography process on a wafer to form a patterned photo resist, and measuring the wafer to determine an overlay error of the patterned photo resist. A high/low specification is determined using the overlay error. An overlay process value setting is generated and compared with the high/low specification to determine whether the overlay process value setting is within a range defined by the high/low specification.
摘要翻译：一种方法包括在晶片上进行光刻工艺以形成图案化光刻胶，并测量晶片以确定图案化光刻胶的重叠误差。使用重叠错误确定高/低规格。生成覆盖过程值设置并与高/低规格进行比较，以确定覆盖过程值设置是否在由高/低规格定义的范围内。

5. 发明授权

US08627251B2 Systems and methods of automatically detecting failure patterns for semiconductor wafer fabrication processes 有权
标题翻译：自动检测半导体晶片制造工艺的故障模式的系统和方法
公开(公告)号：US08627251B2
公开(公告)日：2014-01-07
申请号：US13455186
申请日：2012-04-25
申请人： Jui-Long Chen , Hui-Yun Chao , Yen-Di Tsen , Jong-I Mou
发明人： Jui-Long Chen , Hui-Yun Chao , Yen-Di Tsen , Jong-I Mou
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L22/10 , H01L22/12 , H01L22/14 , H01L2924/0002 , Y10T29/41 , H01L2924/00
摘要： A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.
摘要翻译：提供了一种自动检测半导体晶片工艺的故障模式的系统和方法。该方法包括接收从测试多个半导体晶片收集的测试数据集，为每个晶片形成相应的晶片图，确定每个相应的晶片图是否包括一个或多个相应的对象，选择被确定为包括的晶片图一个或多个相应的对象，选择一个或多个对象索引，用于在每个相应的选定的晶片图中选择相应的对象，确定每个相应选择的晶片图中的多个对象索引值，在每个相应选定的晶片图中选择一个对象，各个所选晶片中的每一个的相应特征，对各个所选晶片图中的每一个分类各自的图案，并使用相应的晶片指纹来调整半导体制造工艺的一个或多个参数。

6. 发明授权

US08205173B2 Physical failure analysis guiding methods 有权
标题翻译：物理故障分析指导方法
公开(公告)号：US08205173B2
公开(公告)日：2012-06-19
申请号：US12818003
申请日：2010-06-17
申请人： Sunny Wu , Yen-Di Tsen , Monghsung Chuang , Fu-Min Huang , Jo Fei Wang , Jong-I Mou
发明人： Sunny Wu , Yen-Di Tsen , Monghsung Chuang , Fu-Min Huang , Jo Fei Wang , Jong-I Mou
IPC分类号： G06F17/50 , G06F19/00 , G06F11/00 , G01R31/00
CPC分类号： G01R31/2894
摘要： A method includes providing a plurality of failure dies, and performing a chip probing on the plurality of failure dies to generate a data log comprising electrical characteristics of the plurality of failure dies. An automatic net tracing is performed to trace failure candidate nodes in the failure dies. A failure layer analysis is performed on results obtained from the automatic net tracing. Physical failure analysis (PFA) samples are selected from the plurality of failure dies using results obtained in the step of performing the failure layer analysis.
摘要翻译：一种方法包括提供多个故障管芯，并对多个故障管芯进行芯片探测以产生包括多个故障管芯的电气特性的数据记录。执行自动网络跟踪以跟踪故障模块中的故障候选节点。对从自动网络跟踪获得的结果执行故障层分析。使用在执行故障层分析的步骤中获得的结果从多个故障模具中选择物理故障分析（PFA）样本。

7. 发明申请

US20120129431A1 APPARATUS AND METHOD FOR TARGET THICKNESS AND SURFACE PROFILE UNIFORMITY CONTROL OF MULTI-HEAD CHEMICAL MECHANICAL POLISHING PROCESS 有权
标题翻译：目标厚度和表面轮廓的设备和方法多头化学机械抛光过程的均匀性控制
公开(公告)号：US20120129431A1
公开(公告)日：2012-05-24
申请号：US12953584
申请日：2010-11-24
申请人： KEUNG HUI , Jin-Ning Sung , Huang Soon Kang , Yen-Di Tsen , Jong-I Mou
发明人： KEUNG HUI , Jin-Ning Sung , Huang Soon Kang , Yen-Di Tsen , Jong-I Mou
IPC分类号： B24B1/00 , B24B51/00
CPC分类号： H01L21/30625 , B24B37/005 , B24B37/042 , B24B37/107 , B24B49/02 , B24B49/04 , B24B49/16 , B24B51/00 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes.
摘要翻译：公开了一种用于提供多头化学机械抛光（CMP）工艺的目标厚度和表面轮廓均匀性控制的装置和方法。一种示例性方法包括提供至少两个晶片; 确定所述至少两个晶片中的每一个的表面轮廓; 基于所述至少两个晶片的表面轮廓确定用于化学机械抛光（CMP）工艺的操作模式; 基于所述操作模式确定所述至少两个晶片中的每一个的CMP抛光配方; 以及基于所确定的CMP抛光配方在所述至少两个晶片上执行CMP处理。

8. 发明申请

US20140033159A1 Method of Optimizing Design for Manufacturing (DFM) 有权
标题翻译：优化制造设计的方法（DFM）
公开(公告)号：US20140033159A1
公开(公告)日：2014-01-30
申请号：US13559081
申请日：2012-07-26
申请人： Keuing Hui , Yen-Wei Cheng , Yen-Di Tsen , Jong-I Mou , Chin-Hsiang Lin
发明人： Keuing Hui , Yen-Wei Cheng , Yen-Di Tsen , Jong-I Mou , Chin-Hsiang Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters.
摘要翻译：本公开描述了优化用于制造（DFM）仿真的设计的方法。该方法包括接收具有特征的集成电路（IC）设计数据，接收具有参数或多个参数的处理数据，执行DFM仿真和优化DFM仿真。执行DFM模拟包括使用IC设计数据和过程数据生成模拟输出数据。优化DFM模拟包括通过DFM仿真生成参数或多个参数的性能指标。优化DFM模拟包括调整外循环，中间循环和内循环的参数或多个参数。优化DFM模拟还包括在参数或多个参数的范围内定位参数或多个参数的性能指标的最低点。

9. 发明授权

US08295965B2 Semiconductor processing dispatch control 有权
标题翻译：半导体处理调度控制
公开(公告)号：US08295965B2
公开(公告)日：2012-10-23
申请号：US12839014
申请日：2010-07-19
申请人： Sunny Wu , Yen-Di Tsen , Chun-Hsien Lin , Keung Hui , Jo Fei Wang , Jong-I Mou
发明人： Sunny Wu , Yen-Di Tsen , Chun-Hsien Lin , Keung Hui , Jo Fei Wang , Jong-I Mou
IPC分类号： G06F19/00 , G01R31/26
CPC分类号： G05B19/4187 , G05B19/042 , G05B19/41865 , G05B2219/2602 , G05B2219/32237 , G05B2219/32423 , G05B2219/45031 , G05B2219/50065 , Y02P90/20
摘要： An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.
摘要翻译：实施例是用于半导体处理控制的方法。该方法包括基于处理的晶片的参数从多个处理阶段识别关键处理阶段，基于该参数来预测由密钥处理阶段处理的晶片的趋势以及多个处理阶段中的一些，以及调度晶片转换为调谐处理阶段中的第一多个工具之一。根据趋势确定第一组多个工具中的一个。

10. 发明申请

US20120028174A1 Defense System in Advanced Process Control 有权
标题翻译：高级过程控制中的防御系统
公开(公告)号：US20120028174A1
公开(公告)日：2012-02-02
申请号：US12844507
申请日：2010-07-27
申请人： Shin-Rung Lu , Chih Ming Hong , Yen-Di Tsen
发明人： Shin-Rung Lu , Chih Ming Hong , Yen-Di Tsen
IPC分类号： G03F7/20
CPC分类号： G03F7/70633 , G03F7/70525
摘要： A method includes performing a lithography process on a wafer to form a patterned photo resist, and measuring the wafer to determine an overlay error of the patterned photo resist. A high/low specification is determined using the overlay error. An overlay process value setting is generated and compared with the high/low specification to determine whether the overlay process value setting is within a range defined by the high/low specification.
摘要翻译：一种方法包括在晶片上进行光刻工艺以形成图案化光刻胶，并测量晶片以确定图案化光刻胶的重叠误差。使用重叠错误确定高/低规格。生成覆盖过程值设置并与高/低规格进行比较，以确定覆盖过程值设置是否在由高/低规格定义的范围内。

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