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1. 发明授权

US08406366B2 Synchronization circuit, synchronization method, and reception system 有权
标题翻译：同步电路，同步方法和接收系统
公开(公告)号：US08406366B2
公开(公告)日：2013-03-26
申请号：US12662669
申请日：2010-04-28
申请人： Masayuki Hattori , Tetsuhiro Futami , Yuichi Hirayama , Keita Izumi
发明人： Masayuki Hattori , Tetsuhiro Futami , Yuichi Hirayama , Keita Izumi
IPC分类号： H04L7/00
CPC分类号： H03L7/22 , H03L7/093
摘要： Disclosed herein is a synchronization circuit including: a first phase-locked loop circuit; a second phase-locked loop circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; and a control circuit.
摘要翻译：这里公开了一种同步电路，包括：第一锁相环电路; 第二锁相环电路; 第一输出电路; 第二输出电路; 第一检测电路; 第二检测电路; 和控制电路。

2. 发明授权

US08385371B2 Frame synchronizer, frame synchronization method and demodulator 有权
标题翻译：帧同步器，帧同步方法和解调器
公开(公告)号：US08385371B2
公开(公告)日：2013-02-26
申请号：US12597527
申请日：2008-04-25
申请人： Hideyuki Matsumoto , Tetsuhiro Futami , Atsushi Makita , Takashi Yokokawa , Doan Tien Dung , Yuichi Mizutani
发明人： Hideyuki Matsumoto , Tetsuhiro Futami , Atsushi Makita , Takashi Yokokawa , Doan Tien Dung , Yuichi Mizutani
IPC分类号： H04J3/06
CPC分类号： H04L7/08 , H04H20/74 , H04H40/90 , H04L27/2656 , H04L27/2675
摘要： A frame synchronizer, frame synchronization method and demodulator which can more positively establish frame synchronization of an input signal which is likely to have a plurality of frame lengths. A differential correlation detector calculates a differential correlation value with no pilot which is associated with the absence of a pilot signal inserted in the input signal and a differential correlation value with a pilot which is associated with the presence of a pilot signal inserted in the input signal. Frame period confirmation counters perform, based on the differential correlation values with no pilot, frame synchronization control appropriate to the input signals whose frame lengths are 21690 and 32490 symbols, respectively. The frame period confirmation counters 1 perform, based on the differential correlation values with a pilot, frame synchronization control appropriate to the input signals whose frame lengths are 22194 and 33282 symbols, respectively.
摘要翻译：一种帧同步器，帧同步方法和解调器，其可以更可靠地建立可能具有多个帧长度的输入信号的帧同步。差分相关检测器计算与无输入信号中插入的导频信号不相关的导频的差分相关值，以及与插入在输入信号中的导频信号的存在相关联的导频的差分相关值。帧周期确认计数器基于不具有导频的差分相关值，分别对帧长度为21690和32490个符号的输入信号进行适合的帧同步控制。帧周期确认计数器1基于与分别具有帧长度为22194和33282个符号的输入信号相适应的具有导频的差分相关值来执行帧同步控制。

3. 发明申请

US20120099635A1 RECEPTION APPARATUS, RECEPTION METHOD, AND PROGRAM 有权
标题翻译：接收装置，接收方法和程序
公开(公告)号：US20120099635A1
公开(公告)日：2012-04-26
申请号：US13235864
申请日：2011-09-19
申请人： Naoki YOSHIMOCHI , Katsumi Takaoka , Tetsuhiro Futami
发明人： Naoki YOSHIMOCHI , Katsumi Takaoka , Tetsuhiro Futami
IPC分类号： H04B1/10 , H04L27/01
CPC分类号： H04L25/0212 , H04L25/03006 , H04L2025/03414 , H04L2025/03484 , H04L2025/03522 , H04L2025/03535 , H04L2025/03611
摘要： Disclosed herein is a reception apparatus including a calculation section and a storage section. The calculation section calculates correlation values between a data sequence included in a known signal and a received signal at a given point in time. The storage section has at least an area sufficient for storing the correlation values calculated for one frame using the received signal which is one frame long and to which the known signal is added.
摘要翻译：这里公开了一种接收装置，包括计算部分和存储部分。计算部分计算包括在已知信号中的数据序列与给定时间点的接收信号之间的相关值。存储部分至少具有足够的区域，用于存储使用一帧长的接收信号为一帧计算的相关值，并且将已知信号添加到该区域。

4. 发明申请

US20120076252A1 SYNCHRONIZING CIRCUIT, SYNCHRONIZING METHOD, AND RECEIVING SYSTEM 失效
标题翻译：同步电路，同步方法和接收系统
公开(公告)号：US20120076252A1
公开(公告)日：2012-03-29
申请号：US13238093
申请日：2011-09-21
申请人： Tetsuhiro FUTAMI , Ikko Okamoto
发明人： Tetsuhiro FUTAMI , Ikko Okamoto
IPC分类号： H03D3/24
CPC分类号： H04L27/2272 , H04L27/0008 , H04L27/0012 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0081
摘要： Disclosed herein is a synchronizing circuit including: a first PLL circuit; a second PLL circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; a control circuit; and a holding section.
摘要翻译：这里公开了一种同步电路，包括：第一PLL电路; 第二PLL电路; 第一输出电路; 第二输出电路; 第一检测电路; 第二检测电路; 一个控制电路; 和一个保持部分。

5. 发明申请

US20100135335A1 FRAME SYNCHRONIZER, FRAME SYNCHRONIZATION METHOD AND DEMODULATOR 有权
标题翻译：框架同步器，框架同步方法和解调器
公开(公告)号：US20100135335A1
公开(公告)日：2010-06-03
申请号：US12597527
申请日：2008-04-25
申请人： Hideyuki Matsumoto , Tetsuhiro Futami , Atsushi Makita , Takashi Yokokawa , Doan Tien Dung , Yuichi Mizutani
发明人： Hideyuki Matsumoto , Tetsuhiro Futami , Atsushi Makita , Takashi Yokokawa , Doan Tien Dung , Yuichi Mizutani
IPC分类号： H04J3/06
CPC分类号： H04L7/08 , H04H20/74 , H04H40/90 , H04L27/2656 , H04L27/2675
摘要： The present invention relates to a frame synchronizer, frame synchronization method and demodulator which can more positively establish frame synchronization of an input signal which is likely to have a plurality of frame lengths.A differential correlation detector 151 calculates a differential correlation value with no pilot which is associated with the absence of a pilot signal inserted in the input signal and a differential correlation value with a pilot which is associated with the presence of a pilot signal inserted in the input signal. The frame period confirmation counters 152-1 and 152-3 perform, based on the differential correlation values with no pilot, frame synchronization control appropriate to the input signals whose frame lengths are 21690 and 32490 symbols, respectively. The frame period confirmation counters 152-2 and 152-4 perform, based on the differential correlation values with a pilot, frame synchronization control appropriate to the input signals whose frame lengths are 22194 and 33282 symbols, respectively.The present invention is applicable, for example, to a satellite broadcast receiver.
摘要翻译：帧同步器，帧同步方法和解调器技术领域本发明涉及帧同步器，帧同步方法和解调器，其可以更可靠地建立可能具有多个帧长度的输入信号的帧同步。差分相关检测器151计算与没有插入在输入信号中的导频信号不相关的导频的差分相关值以及与插入在输入端中的导频信号的存在相关联的导频的差分相关值信号。帧周期确认计数器152-1,152-3分别基于不具有导频的差分相关值，分别对帧长度分别为21690和32490的输入信号进行适合的帧同步控制。帧周期确认计数器152-2,152-4分别基于具有导频的差分相关值，分别对帧长度为22194和33282符号的输入信号进行适合的帧同步控制。本发明可以应用于例如卫星广播接收机。

6. 发明授权

US07609775B2 Radio communication apparatus and communication method 有权
标题翻译：无线电通信装置和通信方法
公开(公告)号：US07609775B2
公开(公告)日：2009-10-27
申请号：US11808541
申请日：2007-06-11
申请人： Dai Kimura , Tetsuhiro Futami , Yoshihiro Kawasaki
发明人： Dai Kimura , Tetsuhiro Futami , Yoshihiro Kawasaki
IPC分类号： H04L27/28 , H04B1/69
CPC分类号： H04L27/2647 , H04L27/2607
摘要： In a radio communication apparatus for forming a frame with a plurality of slots, and inserting a guard interval into each slot along with data for a mobile station to perform communication, a receive state acquisition section acquires a receive state of each mobile station, a frame format decision section decides a frame format of which guard interval length is, different for each slot based on the receive state of each mobile station, a slot assignment section assigns each slot of the frame format to data for each mobile station, and a frame format reporting section reports the decided frame format to the mobile stations via a reporting channel. The mobile station identifies the GI length based on the reported frame format and the slot number, removes the guard interval, and performs processing.
摘要翻译：在用于形成具有多个时隙的帧的无线电通信装置中，并且与用于移动台进行通信的数据一起将保护间隔与每个时隙一起插入，接收状态获取部分获取每个移动台的接收状态，帧格式决定部基于每个移动台的接收状态来决定保护间隔长度对于每个时隙不同的帧格式，时隙分配部将帧格式的每个时隙分配给每个移动台的数据，以及帧格式报告部分通过报告信道将确定的帧格式报告给移动台。移动台基于所报告的帧格式和时隙号识别GI长度，消除保护间隔，并执行处理。

7. 发明申请

US20060007904A1 Apparatus and method for fading frequency estimation 有权
公开(公告)号：US20060007904A1
公开(公告)日：2006-01-12
申请号：US10988411
申请日：2004-11-12
申请人： Tsuyoshi Shimomura , Dai Kimura , Tetsuhiro Futami , Morihiko Minowa
发明人： Tsuyoshi Shimomura , Dai Kimura , Tetsuhiro Futami , Morihiko Minowa
IPC分类号： H04B7/216
CPC分类号： H04L25/0202 , H04B2201/70701 , H04L25/0222
摘要： The invention relates to an apparatus and a method for estimating a fading frequency of incoming received waves in a receiving station of a radio communication system or radio transmission system. An object of the invention is to estimate a fading frequency efficiently and accurately without substantially complexing the configuration of the system. To this end, the invention provides an apparatus for estimating a fading frequency from a pilot signal in a reception signal, which includes a calculation unit for calculating a magnitude of a complex product of two symbols that are received at different instants, and an estimation unit for estimating a fading frequency according to the calculated magnitude of the complex product.

8. 发明授权

US08750424B2 Signal receiving apparatus, signal receiving method and signal receiving program 失效
标题翻译：信号接收装置，信号接收方法和信号接收程序
公开(公告)号：US08750424B2
公开(公告)日：2014-06-10
申请号：US13205781
申请日：2011-08-09
申请人： Tetsuhiro Futami , Keita Izumi
发明人： Tetsuhiro Futami , Keita Izumi
IPC分类号： H03D3/00
CPC分类号： H04L27/227 , H04L25/03006 , H04L25/067 , H04L27/0014 , H04L27/06 , H04L27/3818 , H04L27/3872 , H04L2025/03687 , H04L2027/0057 , H04L2027/0079
摘要： A signal receiving apparatus has: a radius identifying section configured to identify a radius representing a distance from an origin on an IQ plane of signal points each corresponding to a symbol obtained from a received signal modulated by adoption of an APSK modulation method; and a parameter outputting section configured to output a control parameter related to a demodulation or decoding process of the received signal on the basis of the identified radius.
摘要翻译：信号接收装置具有：半径识别部，其被配置为识别与从通过采用APSK调制方法调制的接收信号获得的符号相对应的信号点的IQ平面上的来自原点的距离的半径; 以及参数输出部，被配置为基于所识别的半径来输出与所述接收信号的解调或解码处理有关的控制参数。

9. 发明申请

US20100303186A1 Synchronization circuit, synchronization method, and reception system 有权
标题翻译：同步电路，同步方法和接收系统
公开(公告)号：US20100303186A1
公开(公告)日：2010-12-02
申请号：US12662669
申请日：2010-04-28
申请人： Masayuki Hattori , Tetsuhiro Futami , Yuichi Hirayama , Keita Izumi
发明人： Masayuki Hattori , Tetsuhiro Futami , Yuichi Hirayama , Keita Izumi
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： H03L7/22 , H03L7/093
摘要： Disclosed herein is a synchronization circuit including: a first phase-locked loop circuit; a second phase-locked loop circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; and a control circuit.
摘要翻译：这里公开了一种同步电路，包括：第一锁相环电路; 第二锁相环电路; 第一输出电路; 第二输出电路; 第一检测电路; 第二检测电路; 和控制电路。

10. 发明申请

US20100040086A1 RADIO COMMUNICATION APPARATUS AND COMMUNICATION METHOD 有权
标题翻译：无线电通信设备和通信方法
公开(公告)号：US20100040086A1
公开(公告)日：2010-02-18
申请号：US12606747
申请日：2009-10-27
申请人： Dai KIMURA , Tetsuhiro FUTAMI , Yoshihiro KAWASAKI
发明人： Dai KIMURA , Tetsuhiro FUTAMI , Yoshihiro KAWASAKI
IPC分类号： H04J3/24
CPC分类号： H04L27/2647 , H04L27/2607
摘要： In a radio communication apparatus for forming a frame with a plurality of slots, and inserting a guard interval into each slot along with data for a mobile station to perform communication, a receive state acquisition section acquires a receive state of each mobile station, a frame format decision section decides a frame format of which guard interval length is different for each slot based on the receive state of each mobile station, a slot assignment section assigns each slot of the frame format to data for each mobile station, and a frame format reporting section reports the decided frame format to the mobile stations via a reporting channel. The mobile station identifies the GI length based on the reported frame format and the slot number, removes the guard interval, and performs processing.
摘要翻译：在用于形成具有多个时隙的帧的无线电通信装置中，并且与用于移动台进行通信的数据一起将保护间隔与每个时隙一起插入，接收状态获取部分获取每个移动台的接收状态，帧格式决定部基于各移动台的接收状态来决定各时隙的保护间隔长度不同的帧格式，时隙分配部将帧格式的每个时隙分配给每个移动台的数据，帧格式报告部分通过报告信道将确定的帧格式报告给移动台。移动台基于所报告的帧格式和时隙号识别GI长度，消除保护间隔，并执行处理。

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