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1. 发明授权

US07406495B2 Adder structure with midcycle latch for power reduction 失效
标题翻译：加法器结构带有中间锁闩，用于降低功率
公开(公告)号：US07406495B2
公开(公告)日：2008-07-29
申请号：US10973365
申请日：2004-10-26
申请人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
发明人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
IPC分类号： G06F7/50
CPC分类号： G06F7/506 , G06F7/508 , G06F2207/3872 , H03K19/0941
摘要： A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage with static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.
摘要翻译：一种数字加法器电路，包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数位组，每个级实现预定的逻辑功能，并处理来自前一级的输入变量，并将结果值输出到在4位加法器的进位网络中具有静态和动态逻辑的后级，并且来自第一级的输出直接作为输入（60,62）馈送到进位网络的第三级。优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。

2. 发明授权

US08086657B2 Adder structure with midcycle latch for power reduction 失效
标题翻译：加法器结构带有中间锁闩，用于降低功率
公开(公告)号：US08086657B2
公开(公告)日：2011-12-27
申请号：US12099973
申请日：2008-04-09
申请人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
发明人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
IPC分类号： G06F7/50
CPC分类号： H03K19/0941 , H03K19/0008
摘要： A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.
摘要翻译：一种数字加法器电路，包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数位组，每个级实现预定的逻辑功能，并处理来自前一级的输入变量，并将结果值输出到 4位加法器的进位网络中的后级静态和动态逻辑，并且来自第一级的输出直接作为输入（60,62）馈送到进位网络的第三级。优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。

3. 发明申请

US20080294706A1 Novel Adder Structure with Midcycle Latch for Power Reduction 失效
标题翻译：新型加法器结构与中间锁定功率降低
公开(公告)号：US20080294706A1
公开(公告)日：2008-11-27
申请号：US12099973
申请日：2008-04-09
申请人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
发明人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
IPC分类号： G06F17/10 , G06F7/575
CPC分类号： H03K19/0941 , H03K19/0008
摘要： A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.
摘要翻译：一种数字加法器电路，包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数位组，每个级实现预定的逻辑功能，并处理来自前一级的输入变量，并将结果值输出到 4位加法器的进位网络中的后级静态和动态逻辑，并且来自第一级的输出直接作为输入（60,62）馈送到进位网络的第三级。优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。

4. 发明申请

US20050138103A1 Novel adder structure with midcycle latch for power reduction 失效
标题翻译：用于功率降低的具有中间锁存器的新型加法器结构
公开(公告)号：US20050138103A1
公开(公告)日：2005-06-23
申请号：US10973365
申请日：2004-10-26
申请人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
发明人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
IPC分类号： G06F7/50 , G06F7/506 , G06F7/508 , H03K19/094
CPC分类号： G06F7/506 , G06F7/508 , G06F2207/3872 , H03K19/0941
摘要： The present invention relates to computer processors. In particular it relates to a method and respective system for operating a digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage. In order to reduce power consumption of adders and concurrently increasing adder speed it is proposed to implement a mixture of static and dynamic logic in the carry network of a 4-bit adder, and to feed output from the first stage directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.
摘要翻译：本发明涉及计算机处理器。具体地说，涉及用于操作数字加法器电路的方法和相应系统，该数字加法器电路包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数组组，每个级实现预定的逻辑功能和处理来自前一级的输入变量并将结果值输出到后一级。为了降低加法器的功耗并同时增加加法器速度，提出在4位加法器的进位网络中实现静态和动态逻辑的混合，并将第一级的输出直接作为输入（60 ，62）到进位网络的第三阶段。优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。

5. 发明授权

US07095252B2 Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates 失效
标题翻译：通过在复杂的动态多米诺式CMOS门中应用固有的并行性来减少电荷共享
公开(公告)号：US07095252B2
公开(公告)日：2006-08-22
申请号：US10896836
申请日：2004-07-22
申请人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
发明人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
IPC分类号： H03K19/096 , H03K19/00 , H03K19/20 , H03K19/094
CPC分类号： H03K19/0963
摘要： The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.
摘要翻译：本发明涉及计算机处理器的动态硬件逻辑。特别地，本发明涉及一种用于操作实现具有减少的电荷共享的预定逻辑功能的动态逻辑电路的方法和相应的系统。为了进一步减少电荷共享，建议提供预定数量的预先设计的切换布置（24,26,28），其实现与输入变量（A，B，C）的不同组合分布相同的逻辑功能，其中每个布置连接在较高电位的所述预充电节点和较低电位之间。

6. 发明申请

US20050040861A1 Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates 失效
标题翻译：通过在复杂的动态多米诺式CMOS门中应用固有的并行性来减少电荷共享
公开(公告)号：US20050040861A1
公开(公告)日：2005-02-24
申请号：US10896836
申请日：2004-07-22
申请人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
发明人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
IPC分类号： H03K19/096 , H03K19/20
CPC分类号： H03K19/0963
摘要： The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.
摘要翻译：本发明涉及计算机处理器的动态硬件逻辑。特别地，本发明涉及一种用于操作实现具有减少的电荷共享的预定逻辑功能的动态逻辑电路的方法和相应的系统。为了进一步减少电荷共享，建议提供预定数量的预先设计的切换布置（24,26,28），其实现与输入变量（A，B，C）的不同组合分布相同的逻辑功能，其中每个布置连接在较高电位的所述预充电节点和较低电位之间。

7. 发明申请

US20050134316A1 Midcycle latch for power saving and switching reduction 失效
标题翻译：用于省电和切换的中间锁闩
公开(公告)号：US20050134316A1
公开(公告)日：2005-06-23
申请号：US11009830
申请日：2004-12-10
申请人： Wilhelm Haller , Rolf Sautter , Monika Strohmer , Klaus Thumm
发明人： Wilhelm Haller , Rolf Sautter , Monika Strohmer , Klaus Thumm
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors, and more particularly, to an integrated circuit comprising a dynamic logic function implementing a predetermined logic function with a plurality of transistor stacks, the integrated circuit comprising a precharge node at the input of said logic function implementation, an output latch connected to the output node of said logic function for stabilizing the result of the evaluation of said logic function. The present invention provides such integrated dynamic circuit with a latch, which is protected against instability even in situations involving complex logic functions which are evaluated and their output states are saved by said output latch.
摘要翻译：本发明涉及硬件逻辑电路领域，特别涉及在计算机处理器中实现的动态硬件逻辑，更具体地，涉及一种集成电路，其包括实现具有多个晶体管堆叠的预定逻辑功能的动态逻辑功能，所述集成电路电路包括在所述逻辑功能实现的输入处的预充电节点，连接到所述逻辑功能的输出节点的输出锁存器，用于稳定所述逻辑功能的评估结果。本发明提供了具有锁存器的这种集成动态电路，其即使在涉及复杂逻辑功能的情况下也被保护以防止不稳定性，这些功能被评估，并且其输出状态由所述输出锁存器保存。

8. 发明授权

US07224190B2 Midcycle latch for power saving and switching reduction 失效
标题翻译：用于省电和切换的中间锁闩
公开(公告)号：US07224190B2
公开(公告)日：2007-05-29
申请号：US11009830
申请日：2004-12-10
申请人： Wilhelm Haller , Rolf Sautter , Monika Strohmer , Klaus Thumm
发明人： Wilhelm Haller , Rolf Sautter , Monika Strohmer , Klaus Thumm
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors, and more particularly, to an integrated circuit comprising a dynamic logic function implementing a predetermined logic function with a plurality of transistor stacks, the integrated circuit comprising a precharge node at the input of said logic function implementation, an output latch connected to the output node of said logic function for stabilizing the result of the evaluation of said logic function. The present invention provides such integrated dynamic circuit with a latch, which is protected against instability even in situations involving complex logic functions which are evaluated and their output states are saved by said output latch.
摘要翻译：本发明涉及硬件逻辑电路领域，特别涉及在计算机处理器中实现的动态硬件逻辑，更具体地，涉及一种集成电路，其包括实现具有多个晶体管堆叠的预定逻辑功能的动态逻辑功能，所述集成电路电路包括在所述逻辑功能实现的输入处的预充电节点，连接到所述逻辑功能的输出节点的输出锁存器，用于稳定所述逻辑功能的评估结果。本发明提供了具有锁存器的这种集成动态电路，其即使在涉及复杂逻辑功能的情况下也被保护以防止不稳定性，这些功能被评估，并且其输出状态由所述输出锁存器保存。

9. 发明授权

US07650535B2 Array delete mechanisms for shipping a microprocessor with defective arrays 失效
标题翻译：用于运送有缺陷阵列的微处理器的阵列删除机制
公开(公告)号：US07650535B2
公开(公告)日：2010-01-19
申请号：US11522142
申请日：2006-09-16
申请人： Norbert Hagspiel , William V. Huott , Frank Lehnert , Brian R. Prasky , Richard Rizzolo , Rolf Sautter
发明人： Norbert Hagspiel , William V. Huott , Frank Lehnert , Brian R. Prasky , Richard Rizzolo , Rolf Sautter
IPC分类号： G06F11/00
CPC分类号： G06F11/27 , G06F11/2236
摘要： Detecting and correcting errors in arrays after ABIST testing, after ABIST testing, detected errors are faults are isolated by blowing a fuse.
摘要翻译： ABIST测试后，在ABIST测试后检测和纠正数组中的错误，检测错误是通过吹保险丝来隔离故障。

10. 发明授权

US07295481B2 Power saving by disabling cyclic bitline precharge 有权
标题翻译：通过禁用循环位线预充电节电
公开(公告)号：US07295481B2
公开(公告)日：2007-11-13
申请号：US10711982
申请日：2004-10-18
申请人： Juergen Pille , Rolf Sautter , Christian Schweizer , Klaus Thumm
发明人： Juergen Pille , Rolf Sautter , Christian Schweizer , Klaus Thumm
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C2207/2227
摘要： A method and system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by activating complementary bitlines. A reduction in power dissipation is realized by determining whether a next access operation following a current access operation is a read or write access, and performing a precharge of the bitlines of the array only when a read operation follows the current access operation. A conventional precharge control signal is combined with an external control signal indicating if the next cycle is a read cycle. The combination of the two signals can be used, for example, as input to a simple AND gate to generate an effective precharge signal. The effective precharge signal permits precharging of bitlines only when those bitlines are used for read access in a respective next cycle.
摘要翻译：一种访问由位线预充电电路操作的动态硬件存储器块内的存储器单元的方法和系统，其中通过激活补充位线执行差分读/写访问操作。通过确定当前访问操作之后的下一个访问操作是读取还是写入访问，并且仅当读取操作遵循当前访问操作时才执行阵列的位线的预充电来实现功耗的降低。常规的预充电控制信号与指示下一个周期是否为读周期的外部控制信号组合。两个信号的组合可以用作例如简单与门的输入以产生有效的预充电信号。只有当这些位线用于在相应的下一周期中的读取访问时，有效的预充电信号才允许位线预充电。

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