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1. 发明授权

US08086657B2 Adder structure with midcycle latch for power reduction 失效
标题翻译：加法器结构带有中间锁闩，用于降低功率
公开(公告)号：US08086657B2
公开(公告)日：2011-12-27
申请号：US12099973
申请日：2008-04-09
申请人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
发明人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
IPC分类号： G06F7/50
CPC分类号： H03K19/0941 , H03K19/0008
摘要： A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.
摘要翻译：一种数字加法器电路，包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数位组，每个级实现预定的逻辑功能，并处理来自前一级的输入变量，并将结果值输出到 4位加法器的进位网络中的后级静态和动态逻辑，并且来自第一级的输出直接作为输入（60,62）馈送到进位网络的第三级。优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。

2. 发明授权

US07406495B2 Adder structure with midcycle latch for power reduction 失效
标题翻译：加法器结构带有中间锁闩，用于降低功率
公开(公告)号：US07406495B2
公开(公告)日：2008-07-29
申请号：US10973365
申请日：2004-10-26
申请人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
发明人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
IPC分类号： G06F7/50
CPC分类号： G06F7/506 , G06F7/508 , G06F2207/3872 , H03K19/0941
摘要： A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage with static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.
摘要翻译：一种数字加法器电路，包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数位组，每个级实现预定的逻辑功能，并处理来自前一级的输入变量，并将结果值输出到在4位加法器的进位网络中具有静态和动态逻辑的后级，并且来自第一级的输出直接作为输入（60,62）馈送到进位网络的第三级。优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。

3. 发明申请

US20080294706A1 Novel Adder Structure with Midcycle Latch for Power Reduction 失效
标题翻译：新型加法器结构与中间锁定功率降低
公开(公告)号：US20080294706A1
公开(公告)日：2008-11-27
申请号：US12099973
申请日：2008-04-09
申请人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
发明人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
IPC分类号： G06F17/10 , G06F7/575
CPC分类号： H03K19/0941 , H03K19/0008
摘要： A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.
摘要翻译：一种数字加法器电路，包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数位组，每个级实现预定的逻辑功能，并处理来自前一级的输入变量，并将结果值输出到 4位加法器的进位网络中的后级静态和动态逻辑，并且来自第一级的输出直接作为输入（60,62）馈送到进位网络的第三级。优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。

4. 发明申请

US20050138103A1 Novel adder structure with midcycle latch for power reduction 失效
标题翻译：用于功率降低的具有中间锁存器的新型加法器结构
公开(公告)号：US20050138103A1
公开(公告)日：2005-06-23
申请号：US10973365
申请日：2004-10-26
申请人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
发明人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
IPC分类号： G06F7/50 , G06F7/506 , G06F7/508 , H03K19/094
CPC分类号： G06F7/506 , G06F7/508 , G06F2207/3872 , H03K19/0941
摘要： The present invention relates to computer processors. In particular it relates to a method and respective system for operating a digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage. In order to reduce power consumption of adders and concurrently increasing adder speed it is proposed to implement a mixture of static and dynamic logic in the carry network of a 4-bit adder, and to feed output from the first stage directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.
摘要翻译：本发明涉及计算机处理器。具体地说，涉及用于操作数字加法器电路的方法和相应系统，该数字加法器电路包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数组组，每个级实现预定的逻辑功能和处理来自前一级的输入变量并将结果值输出到后一级。为了降低加法器的功耗并同时增加加法器速度，提出在4位加法器的进位网络中实现静态和动态逻辑的混合，并将第一级的输出直接作为输入（60 ，62）到进位网络的第三阶段。优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。

5. 发明授权

US07095252B2 Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates 失效
标题翻译：通过在复杂的动态多米诺式CMOS门中应用固有的并行性来减少电荷共享
公开(公告)号：US07095252B2
公开(公告)日：2006-08-22
申请号：US10896836
申请日：2004-07-22
申请人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
发明人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
IPC分类号： H03K19/096 , H03K19/00 , H03K19/20 , H03K19/094
CPC分类号： H03K19/0963
摘要： The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.
摘要翻译：本发明涉及计算机处理器的动态硬件逻辑。特别地，本发明涉及一种用于操作实现具有减少的电荷共享的预定逻辑功能的动态逻辑电路的方法和相应的系统。为了进一步减少电荷共享，建议提供预定数量的预先设计的切换布置（24,26,28），其实现与输入变量（A，B，C）的不同组合分布相同的逻辑功能，其中每个布置连接在较高电位的所述预充电节点和较低电位之间。

6. 发明申请

US20050040861A1 Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates 失效
标题翻译：通过在复杂的动态多米诺式CMOS门中应用固有的并行性来减少电荷共享
公开(公告)号：US20050040861A1
公开(公告)日：2005-02-24
申请号：US10896836
申请日：2004-07-22
申请人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
发明人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
IPC分类号： H03K19/096 , H03K19/20
CPC分类号： H03K19/0963
摘要： The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.
摘要翻译：本发明涉及计算机处理器的动态硬件逻辑。特别地，本发明涉及一种用于操作实现具有减少的电荷共享的预定逻辑功能的动态逻辑电路的方法和相应的系统。为了进一步减少电荷共享，建议提供预定数量的预先设计的切换布置（24,26,28），其实现与输入变量（A，B，C）的不同组合分布相同的逻辑功能，其中每个布置连接在较高电位的所述预充电节点和较低电位之间。

7. 发明授权

US5870324A Contents-addressable memory 失效
标题翻译：内容可寻址内存
公开(公告)号：US5870324A
公开(公告)日：1999-02-09
申请号：US750765
申请日：1997-03-07
申请人： Klaus Helwig , Christoph Wandel
发明人： Klaus Helwig , Christoph Wandel
IPC分类号： G11C8/12 , G11C15/04 , G11C7/00
CPC分类号： G11C8/12 , G11C15/04
摘要： The invention relates to a contents-addressable memory (CAM) with multiple logical-memory arrays Di. The logical-memory arrays Di are distributed logically in multiple blocks Dij. The blocks Dij are physically arranged to memory arrays Di' and integrated on the chip surface. Each memory array Di' hereby has one block Dij of the logical memory arrays Di. In this way, parasitic capacities of the CAM may be minimized.
摘要翻译： PCT No.PCT / EP95 / 01460 Sec。 371日期1997年3月7日 102（e）1997年3月7日PCT PCT。1995年4月18日PCT公布。 WO96 / 33499 PCT公开日期1996年10月24日本发明涉及具有多个逻辑存储器阵列Di的内容寻址存储器（CAM）。逻辑存储器阵列Di在逻辑上分布在多个块Dij中。块Dij物理地布置到存储器阵列Di'并且集成在芯片表面上。每个存储器阵列Di'具有逻辑存储器阵列Di的一个块Dij。以这种方式，CAM的寄生电容可以被最小化。

8. 发明申请

US20130145329A1 Incorporating Synthesized Netlists as Subcomponents in a Hierarchical Custom Design 失效
标题翻译：将综合网表列入分层定制设计中的子组件
公开(公告)号：US20130145329A1
公开(公告)日：2013-06-06
申请号：US13312108
申请日：2011-12-06
申请人： Uwe Brandt , Thomas M. Makowski , Christoph Wandel , Holger Wetter
发明人： Uwe Brandt , Thomas M. Makowski , Christoph Wandel , Holger Wetter
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/505
摘要： Mechanisms are provided for generating a physical layout of an integrated circuit design. A logic description of the integrated circuit design is received that comprises a first logic description of an irregular logic block of the integrated circuit design and a second logic description of a regular logic block of the integrated circuit design. A manual design of the regular logic block of the integrated circuit design is performed based on user input and an automated design of the irregular logic block of the integrated circuit design is performed without user input. The manual design of the regular logic block and the automated design of the irregular logic block are then integrated into the integrated circuit design to generate a hybrid integrated circuit design.
摘要翻译：提供用于生成集成电路设计的物理布局的机制。接收集成电路设计的逻辑描述，其包括集成电路设计的不规则逻辑块的第一逻辑描述和集成电路设计的规则逻辑块的第二逻辑描述。基于用户输入执行集成电路设计的常规逻辑块的手动设计，并且在不进行用户输入的情况下执行集成电路设计的不规则逻辑块的自动设计。然后将常规逻辑块的手动设计和不规则逻辑块的自动设计集成到集成电路设计中以产生混合集成电路设计。

9. 发明授权

US08560983B2 Incorporating synthesized netlists as subcomponents in a hierarchical custom design 失效
标题翻译：将综合网表列入分层定制设计中的子组件
公开(公告)号：US08560983B2
公开(公告)日：2013-10-15
申请号：US13312108
申请日：2011-12-06
申请人： Uwe Brandt , Thomas M. Makowski , Christoph Wandel , Holger Wetter
发明人： Uwe Brandt , Thomas M. Makowski , Christoph Wandel , Holger Wetter
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/505
摘要： Mechanisms are provided for generating a physical layout of an integrated circuit design. A logic description of the integrated circuit design is received that comprises a first logic description of an irregular logic block of the integrated circuit design and a second logic description of a regular logic block of the integrated circuit design. A manual design of the regular logic block of the integrated circuit design is performed based on user input and an automated design of the irregular logic block of the integrated circuit design is performed without user input. The manual design of the regular logic block and the automated design of the irregular logic block are then integrated into the integrated circuit design to generate a hybrid integrated circuit design.
摘要翻译：提供用于生成集成电路设计的物理布局的机制。接收集成电路设计的逻辑描述，其包括集成电路设计的不规则逻辑块的第一逻辑描述和集成电路设计的规则逻辑块的第二逻辑描述。基于用户输入执行集成电路设计的常规逻辑块的手动设计，并且在不进行用户输入的情况下执行集成电路设计的不规则逻辑块的自动设计。然后将常规逻辑块的手动设计和不规则逻辑块的自动设计集成到集成电路设计中以产生混合集成电路设计。

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