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1. 发明申请

US20100095087A1 Dynamic Data Driven Alignment and Data Formatting in a Floating-Point SIMD Architecture 有权
标题翻译：浮点数SIMD架构中动态数据驱动对齐和数据格式化
公开(公告)号：US20100095087A1
公开(公告)日：2010-04-15
申请号：US12250584
申请日：2008-10-14
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
IPC分类号： G06F9/06
CPC分类号： G06F9/30036 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/3887
摘要： Mechanisms are provided for dynamic data driven alignment and data formatting in a floating point SIMD architecture. At least two operand inputs are input to a permute unit of a processor. Each operand input contains at least one floating point value upon which a permute operation is to be performed by the permute unit. A control vector input, having a plurality of floating point values that together constitute the control vector input, is input to the permute unit of the processor for controlling the permute operation of the permute unit. The permute unit performs a permute operation on the at least two operand inputs according to a permutation pattern specified by the plurality of floating point values that constitute the control vector input. Moreover, a result output of the permute operation is output from the permute unit to a result vector register of the processor.
摘要翻译：为浮点SIMD架构提供动态数据驱动对齐和数据格式化的机制。至少两个操作数输入被输入到处理器的置换单元。每个操作数输入包含至少一个浮点值，在该浮点值上由置换单元执行置换操作。具有一起构成控制向量输入的多个浮点值的控制矢量输入被输入到处理器的置换单元，用于控制置换单元的置换操作。置换单元根据由构成控制向量输入的多个浮点值指定的置换模式对至少两个操作数输入执行置换操作。此外，置换操作的结果输出从处理单元输出到处理器的结果向量寄存器。

2. 发明申请

US20100095086A1 Dynamically Aligning Enhanced Precision Vectors Based on Addresses Corresponding to Reduced Precision Vectors 失效
标题翻译：基于与精简向量精简对应的地址动态对齐增强精度向量
公开(公告)号：US20100095086A1
公开(公告)日：2010-04-15
申请号：US12250599
申请日：2008-10-14
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/30032 , G06F9/30025 , G06F9/30036 , G06F9/3887
摘要： Mechanisms for aligning enhanced precision vectors based on reduced precision data values are provided. At least one data value, having a first precision type, is received for storing in a vector register. The vector register stores data as a vector having a plurality of vector elements. The first precision type is modified to have a second precision type different in precision than the first precision type to thereby generate at least one modified data value. The at least one modified data value is stored in at least one vector element of the plurality of vector elements. An alignment of the at least one modified data value is determined relative to a boundary of a vector element of the vector register. An alignment operation to re-align the at least one modified data value based on the boundary of the vector element of the vector register is performed.
摘要翻译：提供了基于减少的精度数据值对准增强精度向量的机制。接收具有第一精度类型的至少一个数据值以存储在向量寄存器中。向量寄存器将数据存储为具有多个向量元素的向量。第一精度类型被修改为具有与第一精度类型不同的第二精度类型，从而生成至少一个修改的数据值。所述至少一个修改的数据值存储在所述多个向量元素的至少一个向量元素中。相对于向量寄存器的向量元素的边界确定至少一个经修改的数据值的对齐。执行基于向量寄存器的向量元素的边界来重新对准至少一个修改的数据值的对准操作。

3. 发明申请

US20130246737A1 SIMD Compare Instruction Using Permute Logic for Distributed Register Files 有权
标题翻译： SIMD比较指令使用分布式寄存器文件的权限逻辑
公开(公告)号：US20130246737A1
公开(公告)日：2013-09-19
申请号：US13420699
申请日：2012-03-15
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30021 , G06F9/30036 , G06F9/3838
摘要： Mechanisms, in a data processing system comprising a single instruction multiple data (SIMD) processor, for performing a data dependency check operation on vector element values of at least two input vector registers are provided. Two calls to a simd-check instruction are performed, one with input vector registers having a first order and one with the input vector registers having a different order. The simd-check instruction performs comparisons to determine if any data dependencies are present. Results of the two calls to the simd-check instruction are obtained and used to determine if any data dependencies are present in the at least two input vector registers. Based on the results, the SIMD processor may perform various operations.
摘要翻译：提供了一种包括用于对至少两个输入向量寄存器的向量元素值进行数据相关性检查操作的单指令多数据（SIMD）处理器的数据处理系统中的机制。执行对SIMD检查指令的两次调用，其中一个具有输入向量寄存器具有第一级，一个具有不同顺序的输入向量寄存器。 simd检查指令执行比较以确定是否存在任何数据依赖性。获得对simd检查指令的两次调用的结果，并用于确定至少两个输入向量寄存器中是否存在任何数据依赖性。基于该结果，SIMD处理器可以执行各种操作。

4. 发明授权

US09652231B2 All-to-all permutation of vector elements based on a permutation pattern encoded in mantissa and exponent bits in a floating-point SIMD architecture 有权
公开(公告)号：US09652231B2
公开(公告)日：2017-05-16
申请号：US12250584
申请日：2008-10-14
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
IPC分类号： G06F9/315 , G06F7/76 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/3887
摘要： Mechanisms are provided for dynamic data driven alignment and data formatting in a floating point SIMD architecture. At least two operand inputs are input to a permute unit of a processor. Each operand input contains at least one floating point value upon which a permute operation is to be performed by the permute unit. A control vector input, having a plurality of floating point values that together constitute the control vector input, is input to the permute unit of the processor for controlling the permute operation of the permute unit. The permute unit performs a permute operation on the at least two operand inputs according to a permutation pattern specified by the plurality of floating point values that constitute the control vector input. Moreover, a result output of the permute operation is output from the permute unit to a result vector register of the processor.

5. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

6. 发明授权

US07865693B2 Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type 失效
标题翻译：使用指示相对于精度类型的元素边界的偏移的掩码对齐精确转换的矢量数据
公开(公告)号：US07865693B2
公开(公告)日：2011-01-04
申请号：US12250599
申请日：2008-10-14
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
IPC分类号： G06F15/16
CPC分类号： G06F9/30032 , G06F9/30025 , G06F9/30036 , G06F9/3887
摘要： Mechanisms for aligning enhanced precision vectors based on reduced precision data values are provided. At least one data value, having a first precision type, is received for storing in a vector register. The vector register stores data as a vector having a plurality of vector elements. The first precision type is modified to have a second precision type different in precision than the first precision type to thereby generate at least one modified data value. The at least one modified data value is stored in at least one vector element of the plurality of vector elements. An alignment of the at least one modified data value is determined relative to a boundary of a vector element of the vector register. An alignment operation to re-align the at least one modified data value based on the boundary of the vector element of the vector register is performed.
摘要翻译：提供了基于减少的精度数据值对准增强精度向量的机制。接收具有第一精度类型的至少一个数据值以存储在向量寄存器中。向量寄存器将数据存储为具有多个向量元素的向量。第一精度类型被修改为具有与第一精度类型不同的第二精度类型，从而生成至少一个修改的数据值。所述至少一个修改的数据值存储在所述多个向量元素的至少一个向量元素中。相对于向量寄存器的向量元素的边界确定至少一个经修改的数据值的对齐。执行基于向量寄存器的向量元素的边界来重新对准至少一个修改的数据值的对准操作。

7. 发明授权

US09575753B2 SIMD compare instruction using permute logic for distributed register files 有权
标题翻译： SIMD比较指令使用分布式寄存器文件的置换逻辑
公开(公告)号：US09575753B2
公开(公告)日：2017-02-21
申请号：US13420699
申请日：2012-03-15
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30032 , G06F9/30021 , G06F9/30036 , G06F9/3838
摘要： Mechanisms, in a data processing system comprising a single instruction multiple data (SIMD) processor, for performing a data dependency check operation on vector element values of at least two input vector registers are provided. Two calls to a simd-check instruction are performed, one with input vector registers having a first order and one with the input vector registers having a different order. The simd-check instruction performs comparisons to determine if any data dependencies are present. Results of the two calls to the simd-check instruction are obtained and used to determine if any data dependencies are present in the at least two input vector registers. Based on the results, the SIMD processor may perform various operations.
摘要翻译：提供了一种包括用于对至少两个输入向量寄存器的向量元素值进行数据相关性检查操作的单指令多数据（SIMD）处理器的数据处理系统中的机制。执行对SIMD检查指令的两次调用，其中一个具有输入向量寄存器具有第一级，一个具有不同顺序的输入向量寄存器。 simd检查指令执行比较以确定是否存在任何数据依赖性。获得对simd检查指令的两次调用的结果，并用于确定至少两个输入向量寄存器中是否存在任何数据依赖性。基于该结果，SIMD处理器可以执行各种操作。

8. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

9. 发明授权

US09632778B2 Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry 有权
公开(公告)号：US09632778B2
公开(公告)日：2017-04-25
申请号：US13569363
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an instruction for execution by the processing element. A plurality of individually addressable data elements is gathered from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The processing element packs and loads the data elements into register file elements of a register file entry based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.

10. 发明授权

US09575756B2 Predication in a vector processor 有权
标题翻译：矢量处理器中的预测
公开(公告)号：US09575756B2
公开(公告)日：2017-02-21
申请号：US13569349
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F9/30 , G06F9/38 , G06F15/80 , G11C7/10 , G11C8/12
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/3879 , G06F9/3887 , G06F15/8084 , G11C7/1006 , G11C8/12
摘要： Embodiments relate to vector processor predication in an active memory device. An aspect includes a system for vector processor predication in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method including decoding an instruction with a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions.
摘要翻译：实施例涉及有源存储器件中的矢量处理器预测。一个方面包括用于有源存储器设备中的向量处理器预测的系统。该系统包括有源存储器设备中的存储器和有源存储器设备中的处理元件。处理单元被配置为执行包括用多个子指令解码指令并行执行的方法。一个或多个掩码位从处理元件中的向量掩码寄存器访问。一个或多个掩码位由处理元件应用于与至少一个子指令相关联的处理元件中的单元的谓词操作。

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