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1. 发明申请

US20070190736A1 OVERLAY ALIGNMENT MARK AND ALIGNMENT METHOD FOR THE FABRICATION OF TRENCH-CAPACITOR DRAM DEVICES 有权
标题翻译：覆盖电容器DRAM器件的覆盖对准标记和对准方法
公开(公告)号：US20070190736A1
公开(公告)日：2007-08-16
申请号：US11616849
申请日：2006-12-27
申请人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
发明人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于制造需要高精度AA-DT和GC-DT重叠对准的沟槽电容器DRAM器件。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并刷新沟槽轮廓，从而提高覆盖对准精度和精度。

2. 发明授权

US07723181B2 Overlay alignment mark and alignment method for the fabrication of trench-capacitor dram devices 有权
标题翻译：覆盖对准标记和对准方法，用于制造沟槽电容器电容器
公开(公告)号：US07723181B2
公开(公告)日：2010-05-25
申请号：US11616849
申请日：2006-12-27
申请人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
发明人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于制造需要高精度AA-DT和GC-DT重叠对准的沟槽电容器DRAM器件。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并刷新沟槽轮廓，从而提高覆盖对准精度和精度。

3. 发明授权

US06987053B2 Method of evaluating reticle pattern overlay registration 有权
标题翻译：评估标线图案重叠注册的方法
公开(公告)号：US06987053B2
公开(公告)日：2006-01-17
申请号：US10792345
申请日：2004-03-03
申请人： Wen-Bin Wu , Chih-Yuan Hsiao , Hui-Min Mao
发明人： Wen-Bin Wu , Chih-Yuan Hsiao , Hui-Min Mao
IPC分类号： H01L21/76
CPC分类号： G03F9/7019 , G03F7/70633 , G03F9/7011
摘要： A method for evaluating reticle registration between two reticle patterns. A wafer is defined and etched to form a first exposure pattern, by photolithography with a first reticle having a first reticle pattern thereon. A photoresist layer is formed over the wafer and defined as a second exposure pattern, by photolithography with a second reticle having a second reticle pattern thereon. A deviation value between the first and second exposure patterns is measured by a CD-SEM. The deviation value is calibrated according to the scaling degree and the overlay offset to obtain a registration data. The reticle registration between the two reticle patterns is evaluated based on the registration data.
摘要翻译：一种用于评估两个掩模版图案之间的掩模版配准的方法。通过用其上具有第一掩模版图案的第一掩模版通过光刻来限定和蚀刻晶片以形成第一曝光图案。在晶片上形成光致抗蚀剂层，并通过光刻法将其定义为第二曝光图案，其上具有第二掩模版图案的第二掩模版。通过CD-SEM测量第一和第二曝光图案之间的偏差值。根据缩放程度和覆盖偏移校正偏差值，以获得注册数据。基于登记数据评价两个掩模图案之间的掩模版登记。

4. 发明申请

US20050168740A1 Method of evaluating reticle pattern overlay registration 审中-公开
标题翻译：评估标线图案重叠注册的方法
公开(公告)号：US20050168740A1
公开(公告)日：2005-08-04
申请号：US11090643
申请日：2005-03-25
申请人： Wen-Bin Wu , Chih-Yuan Hsiao , Hui-Min Mao
发明人： Wen-Bin Wu , Chih-Yuan Hsiao , Hui-Min Mao
IPC分类号： G03F7/20 , G03F9/00 , G01B11/00 , G06F17/50
CPC分类号： G03F9/7019 , G03F7/70633 , G03F9/7011
摘要： A method for evaluating reticle registration between two reticle patterns. A wafer is defined and etched to form a first exposure pattern, by photolithography with a first reticle having a first reticle pattern thereon. A photoresist layer is formed over the wafer and defined as a second exposure pattern, by photolithography with a second reticle having a second reticle pattern thereon. A deviation value between the first and second exposure patterns is measured by a CD-SEM. The deviation value is calibrated according to the scaling degree and the overlay offset to obtain a registration data. The reticle registration between the two reticle patterns is evaluated based on the registration data.
摘要翻译：一种用于评估两个掩模版图案之间的掩模版配准的方法。通过用其上具有第一掩模版图案的第一掩模版通过光刻来限定和蚀刻晶片以形成第一曝光图案。在晶片上形成光致抗蚀剂层，并通过光刻法将其定义为第二曝光图案，其上具有第二掩模版图案的第二掩模版。通过CD-SEM测量第一和第二曝光图案之间的偏差值。根据缩放程度和覆盖偏移校正偏差值，以获得注册数据。基于登记数据评价两个掩模图案之间的掩模版登记。

5. 发明申请

US20050048654A1 Method of evaluating reticle pattern overlay registration 有权
公开(公告)号：US20050048654A1
公开(公告)日：2005-03-03
申请号：US10792345
申请日：2004-03-03
申请人： Wen-Bin Wu , Chih-Yuan Hsiao , Hui-Min Mao
发明人： Wen-Bin Wu , Chih-Yuan Hsiao , Hui-Min Mao
IPC分类号： G03F7/20 , G03F9/00 , G01N31/00
CPC分类号： G03F9/7019 , G03F7/70633 , G03F9/7011
摘要： A method for evaluating reticle registration between two reticle patterns. A wafer is defined and etched to form a first exposure pattern, by photolithography with a first reticle having a first reticle pattern thereon. A photoresist layer is formed over the wafer and defined as a second exposure pattern, by photolithography with a second reticle having a second reticle pattern thereon. A deviation value between the first and second exposure patterns is measured by a CD-SEM. The deviation value is calibrated according to the scaling degree and the overlay offset to obtain a registration data. The reticle registration between the two reticle patterns is evaluated based on the registration data.

6. 发明授权

US07915133B2 Method of forming a trench capacitor 有权
标题翻译：形成沟槽电容器的方法
公开(公告)号：US07915133B2
公开(公告)日：2011-03-29
申请号：US11953481
申请日：2007-12-10
申请人： Kuo-Yao Cho , Wen-Bin Wu , Chiang-Lin Shih , Jen-Jui Huang
发明人： Kuo-Yao Cho , Wen-Bin Wu , Chiang-Lin Shih , Jen-Jui Huang
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L29/66181
摘要： A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench.
摘要翻译：提供一种形成环型电容器的方法。该方法包括提供基板; 在所述衬底上形成图案化掩模层，所述图案化掩模层限定环形图案; 通过使用图案化掩模层作为掩模去除衬底，以在衬底中形成环型沟槽; 所述环形沟槽包括内壁和外壁; 并在环形沟槽的内壁和外壁上形成电容器结构。

7. 发明申请

US20080251933A1 METAL INTERCONNECT STRUCTURE 审中-公开
标题翻译：金属互连结构
公开(公告)号：US20080251933A1
公开(公告)日：2008-10-16
申请号：US11845746
申请日：2007-08-27
申请人： Kuo-Yao Cho , Wen-Bin Wu , Chiang-Lin Shih , Chia-Cheng Lin
发明人： Kuo-Yao Cho , Wen-Bin Wu , Chiang-Lin Shih , Chia-Cheng Lin
IPC分类号： H01L23/525 , H01L23/52
CPC分类号： H01L23/528 , H01L27/10891 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： A metal interconnect structure includes a plurality of first plugs adjacent to each other, a first metal line extending in a first direction and contacting each first plug to form a first section with a tapered second section in between, and a second plug adjacent to the second section, both in a second direction normal to the first direction.
摘要翻译：金属互连结构包括彼此相邻的多个第一插塞，第一金属线在第一方向上延伸并接触每个第一插塞以形成第一部分，第一部分之间具有锥形第二部分，第二插头与第二插头相邻在第一方向垂直的第二方向上。

8. 发明授权

US08658051B2 Lithography resolution improving method 有权
标题翻译：光刻分辨率改进方法
公开(公告)号：US08658051B2
公开(公告)日：2014-02-25
申请号：US12119275
申请日：2008-05-12
申请人： Kuo-Yao Cho , Wen-Bin Wu , Ya-Chih Wang , Chiang-Lin Shih , Chao-Wen Lay , Chih-Huang Wu
发明人： Kuo-Yao Cho , Wen-Bin Wu , Ya-Chih Wang , Chiang-Lin Shih , Chao-Wen Lay , Chih-Huang Wu
IPC分类号： C23F1/00 , B44C1/22 , H01L21/306
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338
摘要： A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.
摘要翻译：一种改善半导体上的光刻分辨率的方法，包括提供其上依次形成保护层，第一蚀刻层和光致抗蚀剂层的基板的步骤; 图案化光致抗蚀剂层以形成开口，以便部分地露出第一蚀刻层; 将第一离子注入到所揭示的第一蚀刻层中以形成第一掺杂区域; 以及将第二离子注入到所揭示的第一蚀刻层中以形成第二掺杂区域，其中所述第一掺杂区域与所述第二掺杂区域无关。

9. 发明授权

US06998226B2 Method of forming patterned photoresist layer 有权
标题翻译：形成图案化光刻胶层的方法
公开(公告)号：US06998226B2
公开(公告)日：2006-02-14
申请号：US10193464
申请日：2002-07-10
申请人： Yuan-Hsun Wu , Wen-Bin Wu , Yung Long Hung , Ya Chih Wang
发明人： Yuan-Hsun Wu , Wen-Bin Wu , Yung Long Hung , Ya Chih Wang
IPC分类号： G03F7/38 , G03F7/40
CPC分类号： G03F7/168 , G03F7/091 , G03F7/2022 , G03F7/38 , Y10S430/151
摘要： A method of forming a patterned photoresist layer. First, an anti-reflection coating layer is formed on a substrate. Next, a first bake is performed. A photoresist layer is then formed on the anti-reflection coating layer. Exposure is performed. A second bake is performed, wherein the temperature difference between the first bake and the second bake is about 35 ° C.˜55 ° C. Finally, development is performed. The patterned photoresist layer features have perfect profiles in accordance with this invention.
摘要翻译：形成图案化光致抗蚀剂层的方法。首先，在基板上形成防反射涂层。接下来，进行第一烘焙。然后在抗反射涂层上形成光致抗蚀剂层。曝光进行。进行第二烘烤，其中第一烘烤和第二烘烤之间的温度差为约35℃〜55℃。最后，进行显影。图案化的光致抗蚀剂层特征具有根据本发明的完美的轮廓。

10. 发明申请

US20050127356A1 Test mask structure 有权
标题翻译：测试面罩结构
公开(公告)号：US20050127356A1
公开(公告)日：2005-06-16
申请号：US10732370
申请日：2003-12-11
申请人： Wen-Bin Wu
发明人： Wen-Bin Wu
IPC分类号： G03F1/14 , H01L21/66 , H01L23/58 , H01L29/10
CPC分类号： H01L22/12 , G03F1/44 , G03F7/70625
摘要： Disclosed is a test mask structure. The test mask structure of the present invention comprises at least an array pattern region, in a certain proportion to the final product, having a first pattern density according to the certain proportion; and at least one test mask pattern region having a second pattern density. In the test mask structure of the present invention, the required pattern density is obtained by adjusting the area of the array pattern region and the area of the test mask pattern region according to the first pattern density and the second pattern density.
摘要翻译：公开了一种测试掩模结构。本发明的测试掩模结构至少包括与最终产品一定比例的阵列图案区域，其具有按照一定比例的第一图案密度; 以及具有第二图案密度的至少一个测试掩模图案区域。在本发明的测试掩模结构中，通过根据第一图案密度和第二图案密度调整阵列图案区域的面积和测试掩模图案区域的面积来获得所需的图案密度。

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