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1. 发明授权

US08044449B2 Memory device with a length-controllable channel 有权
标题翻译：具有长度可控通道的存储器
公开(公告)号：US08044449B2
公开(公告)日：2011-10-25
申请号：US12183021
申请日：2008-07-30
申请人： Shian-Jyh Lin , Hung-Chang Liao , Meng-Hung Chen , Chung-Yuan Lee , Pei-Ing Lee
发明人： Shian-Jyh Lin , Hung-Chang Liao , Meng-Hung Chen , Chung-Yuan Lee , Pei-Ing Lee
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain.
摘要翻译：提供存储器件。存储器件包括衬底，具有形成在衬底中的上部和下部的沟槽，形成在沟槽的下部的沟槽电容器，形成在沟槽电容器的侧壁上并且远离衬底的顶表面，形成在衬底中用作源极/漏极的沟槽的上部侧的第一掺杂区域，形成在沟槽中并电连接到第一掺杂区域的导电层，顶部形成在导电层上的电介质层，形成在顶部电介质层上的栅极，形成在栅极两侧和衬底上的外延层，以及形成在外延层的顶部上用作源极/漏极的第二掺杂区域。

2. 发明授权

US07795090B2 Electrical device and method for fabricating the same 有权
标题翻译：电气装置及其制造方法
公开(公告)号：US07795090B2
公开(公告)日：2010-09-14
申请号：US12211815
申请日：2008-09-17
申请人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
发明人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/66553 , H01L21/26586 , H01L27/10876 , H01L29/66621 , H01L29/66659
摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.
摘要翻译：公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。多个沟槽嵌入在半导体衬底的存储器阵列区域中。每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

3. 发明授权

US07723181B2 Overlay alignment mark and alignment method for the fabrication of trench-capacitor dram devices 有权
标题翻译：覆盖对准标记和对准方法，用于制造沟槽电容器电容器
公开(公告)号：US07723181B2
公开(公告)日：2010-05-25
申请号：US11616849
申请日：2006-12-27
申请人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
发明人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于制造需要高精度AA-DT和GC-DT重叠对准的沟槽电容器DRAM器件。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并刷新沟槽轮廓，从而提高覆盖对准精度和精度。

4. 发明授权

US07679137B2 Method for fabricating recessed gate MOS transistor device 有权
标题翻译：凹陷栅极MOS晶体管器件的制造方法
公开(公告)号：US07679137B2
公开(公告)日：2010-03-16
申请号：US11696163
申请日：2007-04-03
申请人： Pei-Ing Lee , Chien-Li Cheng , Shian-Jyh Lin
发明人： Pei-Ing Lee , Chien-Li Cheng , Shian-Jyh Lin
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L27/10861 , H01L27/0629 , H01L27/10876
摘要： A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.
摘要翻译：公开了一种使用TTO多隔离件制造自对准栅极沟槽的方法。提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

5. 发明授权

US07622770B2 Semiconductor device having a trench gate and method of fabricating the same 有权
标题翻译：具有沟槽栅的半导体器件及其制造方法
公开(公告)号：US07622770B2
公开(公告)日：2009-11-24
申请号：US12021969
申请日：2008-01-29
申请人： Jeng-Ping Lin , Pei-Ing Lee
发明人： Jeng-Ping Lin , Pei-Ing Lee
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L29/7834 , H01L27/10876 , H01L29/42368 , H01L29/66621
摘要： A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.
摘要翻译：提供一种制造具有沟槽栅极的半导体器件的方法。首先，提供其上具有沟槽蚀刻掩模的半导体衬底。蚀刻半导体衬底以形成具有第一深度的第一沟槽，使用沟槽蚀刻掩模作为屏蔽。杂质通过第一沟槽掺杂到半导体衬底中以形成掺杂区域。蚀刻第一沟槽下面的掺杂区域和半导体衬底以形成具有大于第一深度的第二深度的第二沟槽，其中第二沟槽具有侧壁和底部。栅极绝缘层形成在第二沟槽的侧壁和底部上。沟槽栅极形成在第二沟槽中。

6. 发明授权

US07563686B2 Method for forming a memory device with a recessed gate 有权
标题翻译：用于形成具有凹入栅极的存储器件的方法
公开(公告)号：US07563686B2
公开(公告)日：2009-07-21
申请号：US11140889
申请日：2005-05-31
申请人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
发明人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
IPC分类号： H01L21/20
CPC分类号： H01L29/66621 , H01L27/10823 , H01L27/10829 , H01L27/1087 , H01L27/10876
摘要： A method for forming a memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor device is formed in each trench. The pad layer is recessed until upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions of the deep trench capacitor devices. The pad layer and the substrate are etched using the spacers and the deep trench capacitor devices as a mask to form a recess, and a recessed gate is formed in the recess.
摘要翻译：公开了一种用于形成具有凹入栅极的存储器件的方法。提供其上具有垫层的衬底。图案化衬垫层和衬底以形成至少两个沟槽。在每个沟槽中形成深沟槽电容器器件。衬垫层凹进直到深沟槽电容器器件的上部露出。间隔件形成在深沟槽电容器器件的上部的侧壁上。使用间隔物和深沟槽电容器器件作为掩模来蚀刻焊盘层和衬底以形成凹部，并且在凹部中形成凹入栅极。

7. 发明申请

US20090166703A1 MEMORY DEVICE WITH A LENGTH-CONTROLLABLE CHANNEL 有权
标题翻译：具有长度可控通道的存储器件
公开(公告)号：US20090166703A1
公开(公告)日：2009-07-02
申请号：US12183021
申请日：2008-07-30
申请人： Shian-Jyh LIN , Hung-Chang LIAO , Meng-Hung CHEN , Chung-Yuan LEE , Pei-Ing LEE
发明人： Shian-Jyh LIN , Hung-Chang LIAO , Meng-Hung CHEN , Chung-Yuan LEE , Pei-Ing LEE
IPC分类号： H01L27/108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain.
摘要翻译：提供存储器件。存储器件包括衬底，具有形成在衬底中的上部和下部的沟槽，形成在沟槽的下部的沟槽电容器，形成在沟槽电容器的侧壁上并且远离衬底的顶表面，形成在衬底中用作源极/漏极的沟槽上部一侧的第一掺杂区域，形成在沟槽中并电连接到第一掺杂区域的导电层，顶部形成在导电层上的电介质层，形成在顶部电介质层上的栅极，形成在栅极两侧和衬底上的外延层，以及形成在外延层的顶部上用作源极/漏极的第二掺杂区域。

8. 发明申请

US20090020798A1 TRANSISTOR STRUCTURE AND METHOD OF MAKING THE SAME 有权
标题翻译：晶体管结构及其制作方法
公开(公告)号：US20090020798A1
公开(公告)日：2009-01-22
申请号：US11949788
申请日：2007-12-04
申请人： Pei-Ing Lee , Shian-Jyh Lin
发明人： Pei-Ing Lee , Shian-Jyh Lin
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/1087 , H01L27/10841
摘要： A transistor structure includes a gate trench. The gate trench includes a bottle-shape bottom. The bottle-shape bottom includes a first conductive material wider than its top. The top includes a second material in a substrate, a gate structure on the gate trench and electrically connected to the first conductive material, a source/drain doping region adjacent to the gate trench and a gate channel between the source/drain doping region.
摘要翻译：晶体管结构包括栅极沟槽。栅极沟槽包括瓶形底部。瓶形底部包括比其顶部更宽的第一导电材料。顶部包括衬底中的第二材料，栅极沟槽上的栅极结构和电连接到第一导电材料，与栅极沟槽相邻的源极/漏极掺杂区域和源极/漏极掺杂区域之间的栅极沟道。

9. 发明授权

US07419882B2 Alignment mark and alignment method for the fabrication of trench-capacitor dram devices 有权
标题翻译：用于制造沟槽电容器的对准标记和对准方法
公开(公告)号：US07419882B2
公开(公告)日：2008-09-02
申请号：US11160683
申请日：2005-07-05
申请人： Yuan-Hsun Wu , An-Hsiung Liu , Chiang-Lin Shih , Pei-Ing Lee , Hui-Min Mao , Lin-Chin Su
发明人： Yuan-Hsun Wu , An-Hsiung Liu , Chiang-Lin Shih , Pei-Ing Lee , Hui-Min Mao , Lin-Chin Su
IPC分类号： H01L21/20
CPC分类号： G03F9/7084 , G03F7/70633 , G03F9/708 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于需要高精度AA-DT对准的沟槽电容器DRAM器件的制造。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并且在AA图案转印之前刷新沟槽轮廓，从而提高晶片对准精度和精度。

10. 发明授权

US07316953B2 Method for forming a recessed gate with word lines 有权
标题翻译：用字线形成凹槽的方法
公开(公告)号：US07316953B2
公开(公告)日：2008-01-08
申请号：US11145728
申请日：2005-06-06
申请人： Pei-Ing Lee
发明人： Pei-Ing Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/10888 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L27/10891 , H01L29/66621 , H01L29/7834
摘要： A method for forming a semiconductor device. A substrate is provided, wherein the substrate has recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches for defining active regions. A layer of dielectric material is formed in the shallow trenches, wherein some of the buried portions serve as buried bit line contacts. Word lines are formed across the recessed gates, wherein at least one of the word lines comprises portions overlapping the recessed gates. At least one of the overlapped portions has a narrower width than at least one of the recessed gates.
摘要翻译：一种形成半导体器件的方法。提供了一种衬底，其中衬底在其中具有凹入栅极和深沟槽电容器器件。显露了深沟槽电容器器件的凹入栅极和上部的突出。间隔件形成在上部和突起的侧壁上。导电材料的埋入部分形成在间隔件之间的空间中。将衬底，间隔物和掩埋部分图案化以形成用于限定有源区域的平行的浅沟槽。在浅沟槽中形成介电材料层，其中一些掩埋部分用作掩埋位线接触。字线形成在凹入的栅极之间，其中至少一个字线包括与凹入栅极重叠的部分。重叠部分中的至少一个具有比凹入栅极中的至少一个更窄的宽度。

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