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1. 发明申请

US20070190736A1 OVERLAY ALIGNMENT MARK AND ALIGNMENT METHOD FOR THE FABRICATION OF TRENCH-CAPACITOR DRAM DEVICES 有权
标题翻译：覆盖电容器DRAM器件的覆盖对准标记和对准方法
公开(公告)号：US20070190736A1
公开(公告)日：2007-08-16
申请号：US11616849
申请日：2006-12-27
申请人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
发明人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于制造需要高精度AA-DT和GC-DT重叠对准的沟槽电容器DRAM器件。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并刷新沟槽轮廓，从而提高覆盖对准精度和精度。

2. 发明授权

US07723181B2 Overlay alignment mark and alignment method for the fabrication of trench-capacitor dram devices 有权
标题翻译：覆盖对准标记和对准方法，用于制造沟槽电容器电容器
公开(公告)号：US07723181B2
公开(公告)日：2010-05-25
申请号：US11616849
申请日：2006-12-27
申请人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
发明人： An-Hsiung Liu , Chiang-Lin Shih , Wen-Bin Wu , Hui-Min Mao , Lin-Chin Su , Pei-Ing Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于制造需要高精度AA-DT和GC-DT重叠对准的沟槽电容器DRAM器件。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并刷新沟槽轮廓，从而提高覆盖对准精度和精度。

3. 发明申请

US20060234440A1 ALIGNMENT MARK AND ALIGNMENT METHOD FOR THE FABRICATION OF TRENCH-CAPACITOR DRAM DEVICES 有权
标题翻译：用于制造TRENCH-CAPACITOR DRAM器件的对准标记和对准方法
公开(公告)号：US20060234440A1
公开(公告)日：2006-10-19
申请号：US11160683
申请日：2005-07-05
申请人： Yuan-Hsun WU , An-Hsiung Liu , Chiang-Lin Shih , Pei-Ing Lee , Hui-Min Mao , Lin-Chin Su
发明人： Yuan-Hsun WU , An-Hsiung Liu , Chiang-Lin Shih , Pei-Ing Lee , Hui-Min Mao , Lin-Chin Su
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： G03F9/7084 , G03F7/70633 , G03F9/708 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于需要高精度AA-DT对准的沟槽电容器DRAM器件的制造。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并且在AA图案转印之前刷新沟槽轮廓，从而提高晶片对准精度和精度。

4. 发明授权

US07419882B2 Alignment mark and alignment method for the fabrication of trench-capacitor dram devices 有权
标题翻译：用于制造沟槽电容器的对准标记和对准方法
公开(公告)号：US07419882B2
公开(公告)日：2008-09-02
申请号：US11160683
申请日：2005-07-05
申请人： Yuan-Hsun Wu , An-Hsiung Liu , Chiang-Lin Shih , Pei-Ing Lee , Hui-Min Mao , Lin-Chin Su
发明人： Yuan-Hsun Wu , An-Hsiung Liu , Chiang-Lin Shih , Pei-Ing Lee , Hui-Min Mao , Lin-Chin Su
IPC分类号： H01L21/20
CPC分类号： G03F9/7084 , G03F7/70633 , G03F9/708 , H01L23/544 , H01L27/1087 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A small-size (w
摘要翻译：提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于需要高精度AA-DT对准的沟槽电容器DRAM器件的制造。利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并且在AA图案转印之前刷新沟槽轮廓，从而提高晶片对准精度和精度。

5. 发明授权

US07932555B2 Transistor structure and method of making the same 有权
标题翻译：晶体管结构及制作方法
公开(公告)号：US07932555B2
公开(公告)日：2011-04-26
申请号：US11949788
申请日：2007-12-04
申请人： Pei-Ing Lee , Shian-Jyh Lin
发明人： Pei-Ing Lee , Shian-Jyh Lin
IPC分类号： H01L29/66
CPC分类号： H01L27/1087 , H01L27/10841
摘要： A transistor structure includes a gate trench. The gate trench includes a bottle-shape bottom. The bottle-shape bottom includes a first conductive material wider than its top. The top includes a second material in a substrate, a gate structure on the gate trench and electrically connected to the first conductive material, a source/drain doping region adjacent to the gate trench and a gate channel between the source/drain doping region.
摘要翻译：晶体管结构包括栅极沟槽。栅极沟槽包括瓶形底部。瓶形底部包括比其顶部更宽的第一导电材料。顶部包括衬底中的第二材料，栅极沟槽上的栅极结构和电连接到第一导电材料，与栅极沟槽相邻的源极/漏极掺杂区域和源极/漏极掺杂区域之间的栅极沟道。

6. 发明授权

US07682902B2 Memory structure and method of making the same 有权
标题翻译：内存结构和制作方法
公开(公告)号：US07682902B2
公开(公告)日：2010-03-23
申请号：US11949786
申请日：2007-12-04
申请人： Ching-Nan Hsiao , Pei-Ing Lee , Ming-Cheng Chang , Chung-Lin Huang , Hsi-Hua Chang , Chih-Hsiang Wu
发明人： Ching-Nan Hsiao , Pei-Ing Lee , Ming-Cheng Chang , Chung-Lin Huang , Hsi-Hua Chang , Chih-Hsiang Wu
IPC分类号： H01L21/336
CPC分类号： H01L27/11534 , H01L21/84 , H01L27/11526 , H01L29/42336 , H01L29/66825 , H01L29/7887
摘要： A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.
摘要翻译：本发明公开的存储器结构的特征在于控制栅极和位于凹槽中的浮栅。一种制造存储器结构的方法包括以下步骤：首先提供具有第一凹槽的衬底。然后，在第一凹槽上形成第一栅极电介质层。第一导电层形成在第一栅极介电层上。之后，蚀刻第一导电层以形成用作第一凹槽的侧壁上的浮动栅极的间隔物。在第一凹槽的底部形成第二凹槽。在间隔物的表面，第二凹槽的侧壁和底部上形成栅极间电介质层。形成为填充第一和第二凹槽的第二导电层。

7. 发明申请

US20080135907A1 SEMICONDUCTOR DEVICE HAVING A TRENCH GATE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有高温闸门的半导体器件及其制造方法
公开(公告)号：US20080135907A1
公开(公告)日：2008-06-12
申请号：US12021969
申请日：2008-01-29
申请人： Jeng-Ping Lin , Pei-Ing Lee
发明人： Jeng-Ping Lin , Pei-Ing Lee
IPC分类号： H01L27/108
CPC分类号： H01L29/7834 , H01L27/10876 , H01L29/42368 , H01L29/66621
摘要： A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.
摘要翻译：提供一种制造具有沟槽栅极的半导体器件的方法。首先，提供其上具有沟槽蚀刻掩模的半导体衬底。蚀刻半导体衬底以形成具有第一深度的第一沟槽，使用沟槽蚀刻掩模作为屏蔽。杂质通过第一沟槽掺杂到半导体衬底中以形成掺杂区域。蚀刻第一沟槽下面的掺杂区域和半导体衬底以形成具有大于第一深度的第二深度的第二沟槽，其中第二沟槽具有侧壁和底部。栅极绝缘层形成在第二沟槽的侧壁和底部上。沟槽栅极形成在第二沟槽中。

8. 发明申请

US20080009112A1 METHOD FOR FORMING A MEMORY DEVICE WITH A RECESSED GATE 有权
标题翻译：用于形成具有阻挡门的存储器件的方法
公开(公告)号：US20080009112A1
公开(公告)日：2008-01-10
申请号：US11858703
申请日：2007-09-20
申请人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
发明人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
IPC分类号： H01L21/8242
CPC分类号： H01L29/66621 , H01L27/10823 , H01L27/10829 , H01L27/1087 , H01L27/10876
摘要： A method for forming a semiconductor memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed on each deep trench capacitor, wherein a top surface level of each protrusion is higher than that of the pad layer. Spacers are formed on sidewalls of the protrusions, and the pad layer and the substrate are etched using the spacers and the protrusions as a mask to form a recess. A recessed gate is formed in the recess.
摘要翻译：公开了一种用于形成具有凹入栅极的半导体存储器件的方法。提供其上具有垫层的衬底。图案化衬垫层和衬底以形成至少两个沟槽。在每个沟槽中形成深沟槽电容器。在每个深沟槽电容器上形成突起，其中每个突起的顶表面水平高于焊盘层的顶表面高度。间隔件形成在突起的侧壁上，并且使用间隔件和突起作为掩模来蚀刻衬垫层和衬底以形成凹部。在凹部中形成凹槽。

9. 发明申请

US20070246755A1 METHOD FOR FABRICATING RECESSED GATE MOS TRANSISTOR DEVICE 有权
标题翻译：用于制造接收栅极MOS晶体管器件的方法
公开(公告)号：US20070246755A1
公开(公告)日：2007-10-25
申请号：US11696163
申请日：2007-04-03
申请人： Pei-Ing Lee , Chien-Li Cheng , Shian-Jyh Lin
发明人： Pei-Ing Lee , Chien-Li Cheng , Shian-Jyh Lin
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L27/10861 , H01L27/0629 , H01L27/10876
摘要： A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.
摘要翻译：公开了一种使用TTO多隔离件制造自对准栅极沟槽的方法。提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

10. 发明申请

US20070190712A1 Semiconductor device having a trench gate and method of fabricating the same 审中-公开
标题翻译：具有沟槽栅的半导体器件及其制造方法
公开(公告)号：US20070190712A1
公开(公告)日：2007-08-16
申请号：US11521639
申请日：2006-09-14
申请人： Shian-Jyh Lin , Chien-Li Cheng , Chung-Yuan Lee , Jeng-Ping Lin , Pei-Ing Lee
发明人： Shian-Jyh Lin , Chien-Li Cheng , Chung-Yuan Lee , Jeng-Ping Lin , Pei-Ing Lee
IPC分类号： H01L21/8234
CPC分类号： H01L29/42376 , H01L29/66621
摘要： A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a trench having a sidewall and a bottom using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the trench to form a doped region. The semiconductor substrate underlying the trench is etched to form an extended portion. A gate insulating layer is formed on the trench and the extended portion. A trench gate is formed in the trench and the extended portion.
摘要翻译：提供一种制造具有沟槽栅极的半导体器件的方法。首先，提供其上具有沟槽蚀刻掩模的半导体衬底。使用沟槽蚀刻掩模作为屏蔽，蚀刻半导体衬底以形成具有侧壁和底部的沟槽。杂质通过沟槽掺杂到半导体衬底中以形成掺杂区域。蚀刻沟槽下方的半导体衬底以形成延伸部分。在沟槽和延伸部分上形成栅极绝缘层。在沟槽和延伸部分中形成沟槽栅极。

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