专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08586960B2 Integrated circuit including vertical diode 有权
公开(公告)号：US08586960B2
公开(公告)日：2013-11-19
申请号：US12142239
申请日：2008-06-19
申请人： Thomas Happ , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
发明人： Thomas Happ , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
IPC分类号： H01L29/06
CPC分类号： H01L27/2481 , G11C13/0004 , G11C2213/72 , H01L27/24 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.

2. 发明申请

US20090200534A1 METHOD FOR FABRICATION OF POLYCRYSTALLINE DIODES FOR RESISTIVE MEMORIES 有权
标题翻译：用于制造电阻记忆体的多晶二极管的方法
公开(公告)号：US20090200534A1
公开(公告)日：2009-08-13
申请号：US12027675
申请日：2008-02-07
申请人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
发明人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
IPC分类号： H01L47/00 , H01L21/36
CPC分类号： H01L27/24 , H01L21/02532 , H01L21/0262 , H01L21/02645 , H01L21/02667 , H01L27/1021 , H01L29/8613
摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要翻译：本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

3. 发明申请

US20090185411A1 INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS 审中-公开
标题翻译：集成电路，包括二极管记忆体
公开(公告)号：US20090185411A1
公开(公告)日：2009-07-23
申请号：US12017581
申请日：2008-01-22
申请人： Thomas Happ , Chung Hon Lam , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
发明人： Thomas Happ , Chung Hon Lam , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
IPC分类号： G11C11/00 , H01L21/06
CPC分类号： H01L27/24 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2213/71 , G11C2213/72
摘要： The integrated circuit includes a first metal line and a first diode coupled to the first metal line. The integrated circuit includes a first resistivity changing material coupled to the first diode and a second metal line coupled to the first resistivity changing material.
摘要翻译：集成电路包括耦合到第一金属线的第一金属线和第一二极管。集成电路包括耦合到第一二极管的第一电阻率变化材料和耦合到第一电阻率变化材料的第二金属线。

4. 发明授权

US07955958B2 Method for fabrication of polycrystalline diodes for resistive memories 有权
标题翻译：制造用于电阻存储器的多晶二极管的方法
公开(公告)号：US07955958B2
公开(公告)日：2011-06-07
申请号：US12027675
申请日：2008-02-07
申请人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
发明人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
IPC分类号： H01L21/20
CPC分类号： H01L27/24 , H01L21/02532 , H01L21/0262 , H01L21/02645 , H01L21/02667 , H01L27/1021 , H01L29/8613
摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要翻译：本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以暴露所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

5. 发明申请

US20090316473A1 INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE 有权
标题翻译：集成电路，包括垂直二极管
公开(公告)号：US20090316473A1
公开(公告)日：2009-12-24
申请号：US12142239
申请日：2008-06-19
申请人： Thomas Happ , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
发明人： Thomas Happ , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
IPC分类号： G11C11/00 , H01L47/00 , H01L21/425
CPC分类号： H01L27/2481 , G11C13/0004 , G11C2213/72 , H01L27/24 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.
摘要翻译：集成电路包括包括隔离区域的衬底，在隔离区域之间的衬底中形成的第一导电线和形成在衬底中的垂直二极管。集成电路包括耦合到垂直二极管的触点和耦合到触点的存储元件。第一导线提供垂直二极管的一部分。

6. 发明授权

US08637844B2 Method for fabrication of crystalline diodes for resistive memories 有权
标题翻译：制造电阻式存储器晶体二极管的方法
公开(公告)号：US08637844B2
公开(公告)日：2014-01-28
申请号：US13097307
申请日：2011-04-29
申请人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
发明人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
IPC分类号： H01L47/00
CPC分类号： H01L27/24 , H01L21/02532 , H01L21/0262 , H01L21/02645 , H01L21/02667 , H01L27/1021 , H01L29/8613
摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要翻译：本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

7. 发明申请

US20110198557A1 METHOD FOR FABRICATION OF CRYSTALLINE DIODES FOR RESISTIVE MEMORIES 有权
标题翻译：用于制造用于电阻记忆体的晶体二极管的方法
公开(公告)号：US20110198557A1
公开(公告)日：2011-08-18
申请号：US13097307
申请日：2011-04-29
申请人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
发明人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
IPC分类号： H01L47/00
CPC分类号： H01L27/24 , H01L21/02532 , H01L21/0262 , H01L21/02645 , H01L21/02667 , H01L27/1021 , H01L29/8613
摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要翻译：本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

8. 发明授权

US08030634B2 Memory array with diode driver and method for fabricating the same 有权
标题翻译：具有二极管驱动器的存储器阵列及其制造方法
公开(公告)号：US08030634B2
公开(公告)日：2011-10-04
申请号：US12060075
申请日：2008-03-31
申请人： Hsiang-Lan Lung , Min Yang , Thomas D. Happ , Bipin Rajendran
发明人： Hsiang-Lan Lung , Min Yang , Thomas D. Happ , Bipin Rajendran
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L27/24
摘要： A memory array with self-centered diode access devices results from a process in which diodes are formed in the fill material, each diode having a lightly-doped first layer of the same conductivity type as the conductive lines; a heavily doped second layer of opposite conductivity type; and a conductive cap. Self-aligned, and self-centered spacers in the self-aligned vias define pores that expose the conductive cap. Memory material is deposited within the pores, the memory material making contact with the conductive cap. A top electrode is formed in contact with the memory material.
摘要翻译：具有自中心二极管接入装置的存储器阵列是由填充材料中形成二极管的过程产生的，每个二极管具有与导电线相同导电类型的轻掺杂第一层; 相反导电类型的重掺杂第二层; 和导电帽。自对准和自对准的自对准通孔中的间隔物限定暴露导电盖的孔。记忆材料沉积在孔内，记忆材料与导电帽接触。形成与记忆材料接触的顶部电极。

9. 发明申请

US20090242865A1 MEMORY ARRAY WITH DIODE DRIVER AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有二极管驱动器的存储器阵列及其制造方法
公开(公告)号：US20090242865A1
公开(公告)日：2009-10-01
申请号：US12060075
申请日：2008-03-31
申请人： Hsiang-Lan Lung , Min Yang , Thomas D. Happ , Bipin Rajendran
发明人： Hsiang-Lan Lung , Min Yang , Thomas D. Happ , Bipin Rajendran
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L27/24
摘要： A method of fabricating a memory array. The method begins with a structure, generally composed of dielectric fill material and having conductive lines formed at its lower portion, and a sacrificial layer formed on its upper surface. Diodes are formed in the fill material, each diode having a lightly-doped first layer of the same conductivity type as the conductive lines; a heavily doped second layer of opposite conductivity type; and a conductive cap. Self-aligned vias are formed over the diodes. Self-aligned, and self-centered spacers in the self-aligned vias define pores that expose the conductive cap. Memory material is deposited within the pores, the memory material making contact with the conductive cap. A top electrode is formed in contact with the memory material.
摘要翻译：一种制造存储器阵列的方法。该方法由通常由介电填充材料构成并且在其下部形成有导电线的结构和在其上表面上形成的牺牲层开始。在填充材料中形成二极管，每个二极管具有与导电线相同的导电类型的轻掺杂的第一层; 相反导电类型的重掺杂第二层; 和导电帽。在二极管上形成自对准的通孔。自对准和自对准的自对准通孔中的间隔物限定暴露导电盖的孔。记忆材料沉积在孔内，记忆材料与导电帽接触。形成与记忆材料接触的顶部电极。

10. 发明授权

US07791057B2 Memory cell having a buried phase change region and method for fabricating the same 有权
标题翻译：具有埋置相变区的存储单元及其制造方法
公开(公告)号：US07791057B2
公开(公告)日：2010-09-07
申请号：US12107573
申请日：2008-04-22
申请人： Hsiang-Lan Lung , Chung Hon Lam , Min Yang , Alejandro G. Schrott
发明人： Hsiang-Lan Lung , Chung Hon Lam , Min Yang , Alejandro G. Schrott
IPC分类号： H01L29/02
CPC分类号： H01L45/143 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/14 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1666
摘要： Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode and has a top surface. A memory element is overlying the bottom electrode and includes a recess portion extending from the top surface of the dielectric to contact the pillar portion of the bottom electrode, wherein the recess portion of the memory element has a width substantially equal to the width of the pillar portion of the bottom electrode. A top electrode is on the memory element.
摘要翻译：描述存储单元以及制造方法。本文所述的存储单元包括底部电极，其包括基部和基部上的柱部，所述柱部的宽度小于基部的宽度。电介质围绕底部电极并具有顶部表面。存储元件覆盖在底部电极上并且包括从电介质的顶表面延伸以与底部电极的柱部分接触的凹部，其中存储元件的凹部具有基本上等于柱的宽度的宽度部分底部电极。顶部电极位于存储元件上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式