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1. 发明授权

US08586960B2 Integrated circuit including vertical diode 有权
公开(公告)号：US08586960B2
公开(公告)日：2013-11-19
申请号：US12142239
申请日：2008-06-19
申请人： Thomas Happ , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
发明人： Thomas Happ , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
IPC分类号： H01L29/06
CPC分类号： H01L27/2481 , G11C13/0004 , G11C2213/72 , H01L27/24 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.

2. 发明申请

US20090200534A1 METHOD FOR FABRICATION OF POLYCRYSTALLINE DIODES FOR RESISTIVE MEMORIES 有权
标题翻译：用于制造电阻记忆体的多晶二极管的方法
公开(公告)号：US20090200534A1
公开(公告)日：2009-08-13
申请号：US12027675
申请日：2008-02-07
申请人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
发明人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
IPC分类号： H01L47/00 , H01L21/36
CPC分类号： H01L27/24 , H01L21/02532 , H01L21/0262 , H01L21/02645 , H01L21/02667 , H01L27/1021 , H01L29/8613
摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要翻译：本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

3. 发明申请

US20090185411A1 INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS 审中-公开
标题翻译：集成电路，包括二极管记忆体
公开(公告)号：US20090185411A1
公开(公告)日：2009-07-23
申请号：US12017581
申请日：2008-01-22
申请人： Thomas Happ , Chung Hon Lam , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
发明人： Thomas Happ , Chung Hon Lam , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
IPC分类号： G11C11/00 , H01L21/06
CPC分类号： H01L27/24 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2213/71 , G11C2213/72
摘要： The integrated circuit includes a first metal line and a first diode coupled to the first metal line. The integrated circuit includes a first resistivity changing material coupled to the first diode and a second metal line coupled to the first resistivity changing material.
摘要翻译：集成电路包括耦合到第一金属线的第一金属线和第一二极管。集成电路包括耦合到第一二极管的第一电阻率变化材料和耦合到第一电阻率变化材料的第二金属线。

4. 发明授权

US07955958B2 Method for fabrication of polycrystalline diodes for resistive memories 有权
标题翻译：制造用于电阻存储器的多晶二极管的方法
公开(公告)号：US07955958B2
公开(公告)日：2011-06-07
申请号：US12027675
申请日：2008-02-07
申请人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
发明人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
IPC分类号： H01L21/20
CPC分类号： H01L27/24 , H01L21/02532 , H01L21/0262 , H01L21/02645 , H01L21/02667 , H01L27/1021 , H01L29/8613
摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要翻译：本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以暴露所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

5. 发明申请

US20090316473A1 INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE 有权
标题翻译：集成电路，包括垂直二极管
公开(公告)号：US20090316473A1
公开(公告)日：2009-12-24
申请号：US12142239
申请日：2008-06-19
申请人： Thomas Happ , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
发明人： Thomas Happ , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
IPC分类号： G11C11/00 , H01L47/00 , H01L21/425
CPC分类号： H01L27/2481 , G11C13/0004 , G11C2213/72 , H01L27/24 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.
摘要翻译：集成电路包括包括隔离区域的衬底，在隔离区域之间的衬底中形成的第一导电线和形成在衬底中的垂直二极管。集成电路包括耦合到垂直二极管的触点和耦合到触点的存储元件。第一导线提供垂直二极管的一部分。

6. 发明授权

US08637844B2 Method for fabrication of crystalline diodes for resistive memories 有权
标题翻译：制造电阻式存储器晶体二极管的方法
公开(公告)号：US08637844B2
公开(公告)日：2014-01-28
申请号：US13097307
申请日：2011-04-29
申请人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
发明人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
IPC分类号： H01L47/00
CPC分类号： H01L27/24 , H01L21/02532 , H01L21/0262 , H01L21/02645 , H01L21/02667 , H01L27/1021 , H01L29/8613
摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要翻译：本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

7. 发明申请

US20110198557A1 METHOD FOR FABRICATION OF CRYSTALLINE DIODES FOR RESISTIVE MEMORIES 有权
标题翻译：用于制造用于电阻记忆体的晶体二极管的方法
公开(公告)号：US20110198557A1
公开(公告)日：2011-08-18
申请号：US13097307
申请日：2011-04-29
申请人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
发明人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
IPC分类号： H01L47/00
CPC分类号： H01L27/24 , H01L21/02532 , H01L21/0262 , H01L21/02645 , H01L21/02667 , H01L27/1021 , H01L29/8613
摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要翻译：本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

8. 发明申请

US20090176354A1 METHOD FOR FABRICATION OF SINGLE CRYSTAL DIODES FOR RESISTIVE MEMORIES 有权
标题翻译：用于制造用于电阻记忆体的单晶二极管的方法
公开(公告)号：US20090176354A1
公开(公告)日：2009-07-09
申请号：US11970100
申请日：2008-01-07
申请人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung
发明人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung
IPC分类号： H01L21/20
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/02689 , H01L27/1021 , H01L27/24 , H01L29/8613
摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.
摘要翻译：本发明在一个实施例中提供了一种制造PN结的方法，该方法包括提供单晶衬底; 在单晶基板上形成绝缘层; 通过所述绝缘层形成通孔以提供所述单晶衬底的暴露部分; 在单晶衬底的至少暴露部分上形成非晶Si; 将至少一部分非晶Si转化为单晶Si; 并在单晶Si中形成掺杂区。在一个实施例中，本发明的二极管与存储器件集成。

9. 发明授权

US07902051B2 Method for fabrication of single crystal diodes for resistive memories 有权
标题翻译：用于制造用于电阻存储器的单晶二极管的方法
公开(公告)号：US07902051B2
公开(公告)日：2011-03-08
申请号：US11970100
申请日：2008-01-07
申请人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung
发明人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung
IPC分类号： H01L21/20 , H01L21/36 , H01L21/331 , H01L21/00
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/02689 , H01L27/1021 , H01L27/24 , H01L29/8613
摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.
摘要翻译：本发明在一个实施例中提供了一种制造PN结的方法，该方法包括提供单晶衬底; 在单晶基板上形成绝缘层; 通过所述绝缘层形成通孔以提供所述单晶衬底的暴露部分; 在单晶衬底的至少暴露部分上形成非晶Si; 将至少一部分非晶Si转化为单晶Si; 并在单晶Si中形成掺杂区。在一个实施例中，本发明的二极管与存储器件集成。

10. 发明申请

US20090001341A1 Phase Change Memory with Tapered Heater 有权
标题翻译：带锥形加热器的相变存储器
公开(公告)号：US20090001341A1
公开(公告)日：2009-01-01
申请号：US11771501
申请日：2007-06-29
申请人： Matthew Breitwisch , Thomas Happ , Eric A. Joseph , Hsiang-Lan Lung , Jan Boris Philipp
发明人： Matthew Breitwisch , Thomas Happ , Eric A. Joseph , Hsiang-Lan Lung , Jan Boris Philipp
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.Another embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element. The element includes at least one bottom electrode; at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; and at least one heater layer on at least a portion of an upper surface of the phase change material layer, wherein the heater layer has a tapered shape such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.
摘要翻译：本发明的实施例包括形成非易失性相变存储器（PCM）单元的方法。该方法包括形成至少一个底部电极; 在所述底部电极的上表面的至少一部分上形成至少一个相变材料层; 在所述相变材料层的上表面的至少一部分上形成至少一个加热层; 并且将加热器层成形为锥形，使得加热器层的上表面的横截面宽度大于与相变材料层接触的加热器层的底表面的横截面宽度。本发明的另一实施例包括可配置为用作非易失性存储元件的相变存储器（PCM）结构。该元件包括至少一个底部电极; 在所述底部电极的上表面的至少一部分上的至少一个相变材料层; 以及在所述相变材料层的上表面的至少一部分上的至少一个加热层，其中所述加热器层具有锥形形状，使得所述加热器层的上表面的横截面宽度比加热器层的底表面的与相变材料层接触的横截面宽度。

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