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1. 发明授权

US09250619B2 Systems and methods of automatic boundary control for semiconductor processes 有权
标题翻译：半导体工艺自动边界控制系统和方法
公开(公告)号：US09250619B2
公开(公告)日：2016-02-02
申请号：US13311601
申请日：2011-12-06
申请人： Chih-Wei Hsu , Mei-Jen Wu , Yen-Di Tsen , Jo Fei Wang , Jong-I Mou , Chin-Hsiang Lin
发明人： Chih-Wei Hsu , Mei-Jen Wu , Yen-Di Tsen , Jo Fei Wang , Jong-I Mou , Chin-Hsiang Lin
IPC分类号： G06F19/00 , G05B19/18 , H01L21/66
CPC分类号： G05B19/18 , G05B2219/45031 , H01L22/20
摘要： A system and method of automatically calculating boundaries for a semiconductor fabrication process. The method includes selecting a first parameter for monitoring during a semiconductor fabrication process. A first set of values for the first parameter are received and a group value of the first set is determined. Each value in the first set of values is normalized. A first weighting factor is selected based on a number of values in the first set. The embodiment also includes generating a first and a second boundary value as a function of the weighting factor, the first set normalized values and the group value of the first set and applying the first and second boundary values to control the semiconductor fabrication process.
摘要翻译：一种自动计算半导体制造工艺边界的系统和方法。该方法包括在半导体制造过程中选择用于监测的第一参数。接收第一参数的第一组值，并确定第一组的组值。第一组值中的每个值都被归一化。基于第一组中的值的数量来选择第一加权因子。该实施例还包括根据加权因子，第一集合归一化值和第一组的组值产生第一和第二边界值，并施加第一和第二边界值以控制半导体制造过程。

2. 发明授权

US07127316B2 Method and system for estimating manufacturing target bias 有权
公开(公告)号：US07127316B2
公开(公告)日：2006-10-24
申请号：US10994078
申请日：2004-11-19
申请人： Yen-Pu Hsu , Cheng Hsien Wei , Mei-Jen Wu
发明人： Yen-Pu Hsu , Cheng Hsien Wei , Mei-Jen Wu
IPC分类号： G06F19/00
CPC分类号： G06Q10/06
摘要： A computer implemented method for estimating manufacturing target bias for products in manufacturing tools. The method first establishes a first data set according to manufacturing target bias history based on a correlation with tools used. The manufacturing tools comprise a first manufacturing tool and other manufacturing tools. Next, a testing operation is executed for a predicted product in the first manufacturing tool to obtain a first predicted manufacturing target bias. Finally, manufacturing target bias of the predicted product in the other manufacturing tools is calculated according to the first data set and the first predicted manufacturing target bias.

3. 发明申请

US20060111803A1 Method and system for estimating manufacturing target bias 有权
标题翻译：估算制造目标偏差的方法和系统
公开(公告)号：US20060111803A1
公开(公告)日：2006-05-25
申请号：US10994078
申请日：2004-11-19
申请人： Yen-Pu Hsu , Cheng Wei , Mei-Jen Wu
发明人： Yen-Pu Hsu , Cheng Wei , Mei-Jen Wu
IPC分类号： G06F19/00
CPC分类号： G06Q10/06
摘要： A computer implemented method for estimating manufacturing target bias for products in manufacturing tools. The method first establishes a first data set according to manufacturing target bias history based on a correlation with tools used. The manufacturing tools comprise a first manufacturing tool and other manufacturing tools. Next, a testing operation is executed for a predicted product in the first manufacturing tool to obtain a first predicted manufacturing target bias. Finally, manufacturing target bias of the predicted product in the other manufacturing tools is calculated according to the first data set and the first predicted manufacturing target bias.
摘要翻译：一种用于估计制造工具中产品的制造目标偏差的计算机实现方法。该方法首先基于与使用的工具的相关性，根据制造目标偏差历史来建立第一数据集。制造工具包括第一制造工具和其他制造工具。接下来，对第一制造工具中的预测产品执行测试操作，以获得第一预测制造目标偏差。最后，根据第一数据集和第一预测制造目标偏差来计算其他制造工具中的预测产品的制造目标偏差。

4. 发明授权

US07588946B2 Controlling system for gate formation of semiconductor devices 有权
标题翻译：半导体器件栅极形成控制系统
公开(公告)号：US07588946B2
公开(公告)日：2009-09-15
申请号：US11188324
申请日：2005-07-25
申请人： Chia-Tsung Tso , Jiun-Hong Lai , Mei-Jen Wu , Li Te Hsu , Pin Chia Su , Po-Zen Chen
发明人： Chia-Tsung Tso , Jiun-Hong Lai , Mei-Jen Wu , Li Te Hsu , Pin Chia Su , Po-Zen Chen
IPC分类号： H01L21/00
CPC分类号： H01L22/12 , H01L21/28123 , H01L21/76224 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.
摘要翻译：控制半导体器件的栅极形成的方法包括通过测量隔离结构的阶跃高度来确定隔离结构的台阶高度与过蚀刻时间之间的相关性，基于台阶高度确定过蚀刻时间，以及使用过蚀刻时间。该方法可以包括蚀刻检查以测量栅极分布并微调栅极形成控制。通过测量晶片上的台阶高度均匀性并调整栅极形成工艺，也可以提高晶片内均匀性。

5. 发明申请

US20070020777A1 Controlling system for gate formation of semiconductor devices 有权
标题翻译：半导体器件栅极形成控制系统
公开(公告)号：US20070020777A1
公开(公告)日：2007-01-25
申请号：US11188324
申请日：2005-07-25
申请人： Chia-Tsung Tso , Jiun-Hong Lai , Mei-Jen Wu , Li Hsu , Pin Su , Po-Zen Chen
发明人： Chia-Tsung Tso , Jiun-Hong Lai , Mei-Jen Wu , Li Hsu , Pin Su , Po-Zen Chen
IPC分类号： H01L21/66 , H01L21/76 , H01L21/302
CPC分类号： H01L22/12 , H01L21/28123 , H01L21/76224 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.
摘要翻译：控制半导体器件的栅极形成的方法包括通过测量隔离结构的阶跃高度来确定隔离结构的台阶高度与过蚀刻时间之间的相关性，基于台阶高度确定过蚀刻时间，以及使用过蚀刻时间。该方法可以包括蚀刻检查以测量栅极分布并微调栅极形成控制。通过测量晶片上的台阶高度均匀性并调整栅极形成工艺，也可以提高晶片内均匀性。

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