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1. 发明授权

US07769981B2 Row of floating point accumulators coupled to respective PEs in uppermost row of PE array for performing addition operation 有权
标题翻译：耦合到PE阵列的最上排中的相应PE的浮点累加器的行，用于执行附加操作
公开(公告)号：US07769981B2
公开(公告)日：2010-08-03
申请号：US12045844
申请日：2008-03-11
申请人： Chun Gi Lyuh , Yil Suk Yang , Se Wan Heo , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Se Hoon Yoo
发明人： Chun Gi Lyuh , Yil Suk Yang , Se Wan Heo , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Se Hoon Yoo
IPC分类号： G06F15/80
CPC分类号： G06F15/8007
摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.
摘要翻译：提供了一种用于支持浮点运算的并行处理器。并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

2. 发明授权

US08731059B2 Apparatus and method for calculating sum of absolute differences for motion estimation of variable block 有权
标题翻译：用于计算可变块运动估计的绝对差和的装置和方法
公开(公告)号：US08731059B2
公开(公告)日：2014-05-20
申请号：US12105745
申请日：2008-04-18
申请人： Yil Suk Yang , Jung Hee Suk , Chun Gi Lyuh , Ik Jae Chun , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Jung Hoon Kim
发明人： Yil Suk Yang , Jung Hee Suk , Chun Gi Lyuh , Ik Jae Chun , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Jung Hoon Kim
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04N7/26 , H04N7/50 , H04N7/36
CPC分类号： H04N19/00521 , H04N19/102 , H04N19/122 , H04N19/134 , H04N19/436 , H04N19/57 , H04N19/61 , H04N19/86
摘要： An apparatus that calculates a Sum of Absolute Differences (SAD) for motion estimation of a variable block capable of parallelly calculating SAD values with respect to multiple current frame macroblocks at a time is presented. The apparatus includes a PE array unit including at least one Processing Element (PE) that is aligned in the form of a matrix, and parallelly calculating a SAD value of at least one pixel provided in multiple serial current frame macroblocks, a local memory including current frame macroblock data, reference frame macroblock data, and reference frame search area data, and transmitting the data to each PE that is provided in the PE array unit, and a controller for making a command for the data that are provided in the local memory to be transmitted corresponding to at least one pixel, on which each PE provided in the PE array unit performs calculation.
摘要翻译：提出了一种计算能够相对于多个当前帧宏块同时计算SAD值的可变块的运动估计的绝对差（SAD）的装置。该装置包括PE阵列单元，该PE阵列单元包括以矩阵的形式排列的至少一个处理元件（PE），并且并行地计算在多个串行当前帧宏块中提供的至少一个像素的SAD值，包括电流帧宏块数据，参考帧宏块数据和参考帧搜索区域数据，并且将数据发送到在PE阵列单元中提供的每个PE，以及用于对提供在本地存储器中的数据进行命令的控制器对应于至少一个像素，其中PE阵列单元中提供的每个PE执行计算。

3. 发明申请

US20080133879A1 SIMD parallel processor with SIMD/SISD/row/column operation modes 审中-公开
标题翻译： SIMD并行处理器采用SIMD / SISD /行/列操作模式
公开(公告)号：US20080133879A1
公开(公告)日：2008-06-05
申请号：US11906381
申请日：2007-10-01
申请人： Yil Suk Yang , Tae Moon Roh , Dae Woo Lee , Jong Dae Kim , Chun Gi Lyuh
发明人： Yil Suk Yang , Tae Moon Roh , Dae Woo Lee , Jong Dae Kim , Chun Gi Lyuh
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30036 , G06F9/30098 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/30181 , G06F9/30189
摘要： Provided is a single instruction multiple data (SIMD) parallel processor including a plurality of processing units connected to one another. Each processing unit includes: an instruction register; an instruction decoder; a register files selection circuit; and register files. The SIMD parallel processor can selectively control data of register files required for any one of SIMD, single instruction single data (SISD), row, and column operations in response to an instruction. Since each of the SIMD, SISD, row, and column operations can be effectively performed according to the type of application, the SIMD parallel processor has excellent utility, efficiency, and flexibility.
摘要翻译：提供了包括彼此连接的多个处理单元的单指令多数据（SIMD）并行处理器。每个处理单元包括：指令寄存器; 指令解码器; 寄存器文件选择电路; 并注册文件。 SIMD并行处理器可以选择性地控制响应于指令的SIMD，单指令单数据（SISD），行和列操作中的任何一个所需的寄存器文件的数据。由于可以根据应用类型有效地执行SIMD，SISD，行和列操作，所以SIMD并行处理器具有优异的效用，效率和灵活性。

4. 发明授权

US08150903B2 Reconfigurable arithmetic unit and high-efficiency processor having the same 有权
标题翻译：可重构算术单元和具有相同功能的高效处理器
公开(公告)号：US08150903B2
公开(公告)日：2012-04-03
申请号：US12136107
申请日：2008-06-10
申请人： Yil Suk Yang , Jung Hee Suk , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
发明人： Yil Suk Yang , Jung Hee Suk , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F7/57
CPC分类号： G06F7/57 , G06F7/5324 , G06F7/5338
摘要： Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware.
摘要翻译：提供了一种可重构运算单元和具有该可重配置运算单元的处理器。可重构算术单元可以通过共享加法器来执行根据指令的相加操作或乘法运算。可重构算术单元包括用于编码乘数的展位编码器，用于使用编码乘数产生多个部分乘积的部分乘积生成器和被乘数，用于将部分乘积压缩为第一部分乘积的华莱士树电路和第二部分乘积产品，用于根据选择信号选择和输出第一部分积和第一加法输入之一的第一多路复用器（MUX），用于根据选择信号选择和输出第二部分乘积和第二加法输入之一的第二MUX 选择信号和用于添加第一MUX的输出和第二MUX的输出的进位传播加法器（CPA），以输出运算结果。算术单元可以根据指令作为加法器或乘法器进行操作，从而可以增加整个硬件的使用程度。

5. 发明授权

US07576582B2 Low-power clock gating circuit 有权
标题翻译：低功耗时钟门控电路
公开(公告)号：US07576582B2
公开(公告)日：2009-08-18
申请号：US11945387
申请日：2007-11-27
申请人： Dae Woo Lee , Yil Suk Yang , Ik Jae Chun , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
发明人： Dae Woo Lee , Yil Suk Yang , Ik Jae Chun , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
IPC分类号： H03K3/289
CPC分类号： H03K3/0375
摘要： Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.
摘要翻译：提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用单阈值电压。

6. 发明授权

US07958179B2 Arithmetic method and device of reconfigurable processor 失效
标题翻译：可重构处理器的算术方法和装置
公开(公告)号：US07958179B2
公开(公告)日：2011-06-07
申请号：US11978878
申请日：2007-10-30
申请人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
发明人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F7/38
CPC分类号： G06F7/57
摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.
摘要翻译：提供了可重构处理器的算术方法和装置。算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从ALU，乘法器和移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

7. 发明申请

US20080140745A1 Arithmetic method and device of reconfigurable processor 失效
标题翻译：可重构处理器的算术方法和装置
公开(公告)号：US20080140745A1
公开(公告)日：2008-06-12
申请号：US11978878
申请日：2007-10-30
申请人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
发明人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F5/01
CPC分类号： G06F7/57
摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.
摘要翻译：提供了可重构处理器的算术方法和装置。算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从所述ALU，所述乘法器和所述移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

8. 发明申请

US20110153878A1 MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS 有权
标题翻译：用于DMA通道多重的存储系统和集成管理方法
公开(公告)号：US20110153878A1
公开(公告)日：2011-06-23
申请号：US12882141
申请日：2010-09-14
申请人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

9. 发明申请

US20120226831A1 MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS 审中-公开
标题翻译：用于DMA通道多重的存储系统和集成管理方法
公开(公告)号：US20120226831A1
公开(公告)日：2012-09-06
申请号：US13471236
申请日：2012-05-14
申请人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

10. 发明授权

US08205021B2 Memory system and integrated management method for plurality of DMA channels 有权
标题翻译：用于多个DMA通道的存储系统和集成管理方法
公开(公告)号：US08205021B2
公开(公告)日：2012-06-19
申请号：US12882141
申请日：2010-09-14
申请人： Ik Jae Chun , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae Chun , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

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