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1. 发明授权

US07769981B2 Row of floating point accumulators coupled to respective PEs in uppermost row of PE array for performing addition operation 有权
标题翻译：耦合到PE阵列的最上排中的相应PE的浮点累加器的行，用于执行附加操作
公开(公告)号：US07769981B2
公开(公告)日：2010-08-03
申请号：US12045844
申请日：2008-03-11
申请人： Chun Gi Lyuh , Yil Suk Yang , Se Wan Heo , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Se Hoon Yoo
发明人： Chun Gi Lyuh , Yil Suk Yang , Se Wan Heo , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Se Hoon Yoo
IPC分类号： G06F15/80
CPC分类号： G06F15/8007
摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.
摘要翻译：提供了一种用于支持浮点运算的并行处理器。并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

2. 发明授权

US07958179B2 Arithmetic method and device of reconfigurable processor 失效
标题翻译：可重构处理器的算术方法和装置
公开(公告)号：US07958179B2
公开(公告)日：2011-06-07
申请号：US11978878
申请日：2007-10-30
申请人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
发明人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F7/38
CPC分类号： G06F7/57
摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.
摘要翻译：提供了可重构处理器的算术方法和装置。算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从ALU，乘法器和移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

3. 发明申请

US20080140745A1 Arithmetic method and device of reconfigurable processor 失效
标题翻译：可重构处理器的算术方法和装置
公开(公告)号：US20080140745A1
公开(公告)日：2008-06-12
申请号：US11978878
申请日：2007-10-30
申请人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
发明人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F5/01
CPC分类号： G06F7/57
摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.
摘要翻译：提供了可重构处理器的算术方法和装置。算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从所述ALU，所述乘法器和所述移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

4. 发明申请

US20070150763A1 Highly energy-efficient processor employing dynamic voltage scaling 有权
标题翻译：采用动态电压调节的高能效处理器
公开(公告)号：US20070150763A1
公开(公告)日：2007-06-28
申请号：US11520177
申请日：2006-09-13
申请人： Yil Suk Yang , Jong Dae Kim , Soon Il Yeo , Chun Gi Lyuh
发明人： Yil Suk Yang , Jong Dae Kim , Soon Il Yeo , Chun Gi Lyuh
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/3293 , G06F1/3296 , Y02D10/122 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.A highly energy-efficient processor employing the processor architecture includes: a function unit block for performing an operation according to instructions input from the outside; at least one peripheral unit block for performing data communication with an external device; an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and peripheral unit block required for executing the interpreted instructions; a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; and a peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.
摘要翻译：提供了一种高能效的处理器架构。该架构采用2级动态电压调节（DVS）和睡眠模式以实现高能效，通过指令动态控制电源电压和嵌入式处理器的激活，从而可以在降低功耗的同时防止性能下降。采用该处理器架构的高能效处理器包括：功能单元块，用于根据从外部输入的指令进行操作; 用于与外部设备进行数据通信的至少一个外围单元块; 用于解释输入指令并确定执行解释指令所需的功能单元块和外围单元块的操作模式的指令解码器; 功能单元块驱动器，用于根据功能单元块的操作模式将不同的电源电压施加到功能单元块; 以及外围单元块驱动器，用于根据外围单元块的操作模式向外围单元块施加不同的电源电压。

5. 发明授权

US07805620B2 Highly energy-efficient processor employing dynamic voltage scaling 有权
标题翻译：采用动态电压调节的高能效处理器
公开(公告)号：US07805620B2
公开(公告)日：2010-09-28
申请号：US11520177
申请日：2006-09-13
申请人： Yil Suk Yang , Jong Dae Kim , Soon Il Yeo , Chun Gi Lyuh
发明人： Yil Suk Yang , Jong Dae Kim , Soon Il Yeo , Chun Gi Lyuh
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/3293 , G06F1/3296 , Y02D10/122 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.A highly energy-efficient processor employing the processor architecture includes: a function unit block for performing an operation according to instructions input from the outside; at least one peripheral unit block for performing data communication with an external device; an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and peripheral unit block required for executing the interpreted instructions; a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; and a peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.
摘要翻译：提供了一种高能效的处理器架构。该架构采用2级动态电压调节（DVS）和睡眠模式以实现高能效，通过指令动态控制电源电压和嵌入式处理器的激活，从而可以在降低功耗的同时防止性能下降。采用该处理器架构的高能效处理器包括：功能单元块，用于根据从外部输入的指令进行操作; 用于与外部设备进行数据通信的至少一个外围单元块; 用于解释输入指令并确定执行解释指令所需的功能单元块和外围单元块的操作模式的指令解码器; 功能单元块驱动器，用于根据功能单元块的操作模式将不同的电源电压施加到功能单元块; 以及外围单元块驱动器，用于根据外围单元块的操作模式向外围单元块施加不同的电源电压。

6. 发明申请

US20110022767A1 DMA CONTROLLER WITH INTERRUPT CONTROL PROCESSOR 审中-公开
标题翻译：具有中断控制处理器的DMA控制器
公开(公告)号：US20110022767A1
公开(公告)日：2011-01-27
申请号：US12843801
申请日：2010-07-26
申请人： Ik Jae CHUN , Chun Gi Lyuh , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28 , G06F13/24
CPC分类号： G06F13/32
摘要： Provided is a direct memory access (DMA) controller having an interrupt control processor that can process DMA transmission-related interrupts according to a control program modifiable by a user. The DMA controller includes the interrupt control processor that can process a DMA transmission-related interrupt and a DMA request interrupt transmitted from peripheral devices and control the DMA channel through the control program that can be modified by the user, so that DMA channel control and relevant interrupt processing loads caused by a plurality of DMA data transmissions are reduced, and the flexibility of DMA channel control and interrupt processing in control of the DMA controller is provided to the user.
摘要翻译：提供了具有中断控制处理器的直接存储器访问（DMA）控制器，其可以根据用户可修改的控制程序来处理与DMA传输相关的中断。 DMA控制器包括可处理DMA传输相关中断的中断控制处理器和从外围设备发送的DMA请求中断，并通过可由用户修改的控制程序控制DMA通道，从而使DMA通道控制和相关减少由多个DMA数据传输引起的中断处理负载，并且向用户提供DMA控制的DMA通道控制和中断处理的灵活性。

7. 发明申请

US20080133879A1 SIMD parallel processor with SIMD/SISD/row/column operation modes 审中-公开
标题翻译： SIMD并行处理器采用SIMD / SISD /行/列操作模式
公开(公告)号：US20080133879A1
公开(公告)日：2008-06-05
申请号：US11906381
申请日：2007-10-01
申请人： Yil Suk Yang , Tae Moon Roh , Dae Woo Lee , Jong Dae Kim , Chun Gi Lyuh
发明人： Yil Suk Yang , Tae Moon Roh , Dae Woo Lee , Jong Dae Kim , Chun Gi Lyuh
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30036 , G06F9/30098 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/30181 , G06F9/30189
摘要： Provided is a single instruction multiple data (SIMD) parallel processor including a plurality of processing units connected to one another. Each processing unit includes: an instruction register; an instruction decoder; a register files selection circuit; and register files. The SIMD parallel processor can selectively control data of register files required for any one of SIMD, single instruction single data (SISD), row, and column operations in response to an instruction. Since each of the SIMD, SISD, row, and column operations can be effectively performed according to the type of application, the SIMD parallel processor has excellent utility, efficiency, and flexibility.
摘要翻译：提供了包括彼此连接的多个处理单元的单指令多数据（SIMD）并行处理器。每个处理单元包括：指令寄存器; 指令解码器; 寄存器文件选择电路; 并注册文件。 SIMD并行处理器可以选择性地控制响应于指令的SIMD，单指令单数据（SISD），行和列操作中的任何一个所需的寄存器文件的数据。由于可以根据应用类型有效地执行SIMD，SISD，行和列操作，所以SIMD并行处理器具有优异的效用，效率和灵活性。

8. 发明授权

US08407276B2 Apparatus for calculating absolute difference 有权
标题翻译：用于计算绝对差的装置
公开(公告)号：US08407276B2
公开(公告)日：2013-03-26
申请号：US12843550
申请日：2010-07-26
申请人： Chun Gi Lyuh , Ik Jae Chun , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Chun Gi Lyuh , Ik Jae Chun , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F7/50
CPC分类号： G06F7/544
摘要： Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference includes a comparator comparing values of two integers, first and second selectors each selecting and outputting one of the two integers according to the comparison results of the comparator, an inverter complementing the result value selected by the second selector; and an adder adding up the result value selected by the first selector, the value complemented by the inverter, and 1.
摘要翻译：提供了一种用于计算能够使用加法器有效地执行绝对差的绝对差的装置。用于计算绝对差的装置包括比较器，比较器比较两个整数的值，第一和第二选择器，每个选择器根据比较器的比较结果选择和输出两个整数中的一个;逆变器，补偿由第二选择器选择的结果值; 和加法器将由第一选择器选择的结果值相加，由逆变器补充的值，以及1。

9. 发明申请

US20120226831A1 MEMORY SYSTEM AND INTEGRATED MANAGEMENT METHOD FOR PLURALITY OF DMA CHANNELS 审中-公开
标题翻译：用于DMA通道多重的存储系统和集成管理方法
公开(公告)号：US20120226831A1
公开(公告)日：2012-09-06
申请号：US13471236
申请日：2012-05-14
申请人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Ik Jae CHUN , Chun Gi Lyuh , Se Wan Heo , Sang Hun Yoon , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.
摘要翻译：提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

10. 发明申请

US20110142345A1 APPARATUS AND METHOD FOR RECOGNIZING IMAGE 审中-公开
标题翻译：用于识别图像的装置和方法
公开(公告)号：US20110142345A1
公开(公告)日：2011-06-16
申请号：US12783180
申请日：2010-05-19
申请人： Sang Hun Yoon , Ik Jae Chun , Chun Gi Lyuh , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
发明人： Sang Hun Yoon , Ik Jae Chun , Chun Gi Lyuh , Jung Hee Suk , Tae Moon Roh , Jong Kee Kwon , Jong Dae Kim
IPC分类号： G06K9/46
CPC分类号： G06K9/4614
摘要： Provided are an apparatus and method for recognizing an image. In the apparatus and method for recognizing an image, various features can be extracted by a Haar-like filter using 1st to nth order gradients of the x- and y-axis of an input image, and the input image is correctly classified as a true or false image using, in stages, the extracted features of the input image, multiple threshold values for a true image and multiple threshold values for a false image. Accordingly, the apparatus and method achieve a high recognition rate by performing a small amount of computation. Consequently, it is possible to rapidly and correctly recognize an image, enabling real-time image recognition.
摘要翻译：提供了一种用于识别图像的装置和方法。在用于识别图像的装置和方法中，可以通过输入图像的x轴和y轴的第1至n阶梯度的Haar样滤波器提取各种特征，并且输入图像被正确地分类为真或分别使用输入图像的提取特征，用于真实图像的多个阈值和用于假图像的多个阈值的假图像。因此，该装置和方法通过执行少量的计算来实现高识别率。因此，可以快速且正确地识别图像，从而实现图像识别。

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