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1. 发明授权

US07816215B2 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US07816215B2
公开(公告)日：2010-10-19
申请号：US10941814
申请日：2004-09-16
申请人： Daisuke Matsushita , Koichi Muraoka , Seiji Inumiya , Koichi Kato , Kazuhiro Eguchi , Mariko Takayanagi , Yasushi Nakasaki
发明人： Daisuke Matsushita , Koichi Muraoka , Seiji Inumiya , Koichi Kato , Kazuhiro Eguchi , Mariko Takayanagi , Yasushi Nakasaki
IPC分类号： H01L21/336
CPC分类号： H01L21/28202 , H01L21/022 , H01L21/02329 , H01L21/0234 , H01L21/3144 , H01L29/513 , H01L29/518
摘要： A semiconductor device manufacturing method comprises: forming a gate insulative film on a semiconductor substrate by: forming a first nitride film on the substrate; forming a first oxide film and a second oxide film, the first oxide film being between the substrate and the first nitride film, the second oxide film being on the first nitride film; and nitriding the second oxide film to form, on the first nitride film, one of either: a second nitride film or an SiON film; and forming a gate electrode on the gate insulative film; wherein the equivalent oxide thickness of the gate insulative film is equal to or less than 1 nm.
摘要翻译：一种半导体器件制造方法，包括：在半导体衬底上形成栅极绝缘膜，方法是在衬底上形成第一氮化物膜; 形成第一氧化物膜和第二氧化物膜，所述第一氧化膜位于所述衬底和所述第一氮化物膜之间，所述第二氧化物膜位于所述第一氮化物膜上; 并且对所述第二氧化物膜进行氮化以在所述第一氮化物膜上形成以下之一：第二氮化物膜或SiON膜; 并在所述栅极绝缘膜上形成栅电极; 其中所述栅绝缘膜的等效氧化物厚度等于或小于1nm。

2. 发明申请

US20050064667A1 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US20050064667A1
公开(公告)日：2005-03-24
申请号：US10941814
申请日：2004-09-16
申请人： Daisuke Matsushita , Koichi Muraoka , Seiji Inumiya , Koichi Kato , Kazuhiro Eguchi , Mariko Takayanagi , Yasushi Nakasaki
发明人： Daisuke Matsushita , Koichi Muraoka , Seiji Inumiya , Koichi Kato , Kazuhiro Eguchi , Mariko Takayanagi , Yasushi Nakasaki
IPC分类号： H01L21/318 , H01L21/00 , H01L21/28 , H01L21/314 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/84 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28202 , H01L21/022 , H01L21/02329 , H01L21/0234 , H01L21/3144 , H01L29/513 , H01L29/518
摘要： A semiconductor device manufacturing method comprises: forming a first nitride film on a semiconductor substrate; forming a first oxide film between said semiconductor substrate and said nitride film and forming a second oxide film on said nitride film; forming a second nitride film or an oxide and nitride film on said first nitride film by nitriding said second oxide film; and forming a gate electrode on a gate insulative film including said first oxide film, said first nitride film, and said second nitride film or said oxide and nitride film.
摘要翻译：半导体器件制造方法包括：在半导体衬底上形成第一氮化物膜; 在所述半导体衬底和所述氮化物膜之间形成第一氧化物膜，并在所述氮化膜上形成第二氧化膜; 通过氮化所述第二氧化物膜在所述第一氮化物膜上形成第二氮化物膜或氧化物和氮化物膜; 以及在包括所述第一氧化物膜，所述第一氮化物膜和所述第二氮化物膜或所述氧化物和氮化物膜的栅极绝缘膜上形成栅电极。

3. 发明授权

US08958574B2 Strain and pressure sensing device, microphone, method for manufacturing strain and pressure sensing device, and method for manufacturing microphone 有权
标题翻译：应变和压力感测装置，麦克风，制造应变和压力感测装置的方法以及制造麦克风的方法
公开(公告)号：US08958574B2
公开(公告)日：2015-02-17
申请号：US13536002
申请日：2012-06-28
申请人： Hideaki Fukuzawa , Tatsuya Ohguro , Akihiro Kojima , Yoshiaki Sugizaki , Mariko Takayanagi , Yoshihiko Fuji , Akio Hori , Michiko Hara
发明人： Hideaki Fukuzawa , Tatsuya Ohguro , Akihiro Kojima , Yoshiaki Sugizaki , Mariko Takayanagi , Yoshihiko Fuji , Akio Hori , Michiko Hara
IPC分类号： H04R3/00 , G01L9/00 , H04R1/08 , B81C1/00 , H04R19/00 , H04R19/04 , H04R31/00
CPC分类号： B81C1/00158 , B81B2201/0264 , B81C1/00246 , B81C2203/0771 , G01L9/0042 , H04R1/08 , H04R19/005 , H04R19/04 , H04R31/00
摘要： According to one embodiment, a strain and pressure sensing device includes a semiconductor circuit unit and a sensing unit. The semiconductor circuit unit includes a semiconductor substrate and a transistor. The transistor is provided on a semiconductor substrate. The sensing unit is provided on the semiconductor circuit unit, and has space and non-space portions. The non-space portion is juxtaposed with the space portion. The sensing unit further includes a movable beam, a strain sensing element unit, and first and second buried interconnects. The movable beam has fixed and movable portions, and includes first and second interconnect layers. The fixed portion is fixed to the non-space portion. The movable portion is separated from the transistor and extends from the fixed portion into the space portion. The strain sensing element unit is fixed to the movable portion. The first and second buried interconnects are provided in the non-space portion.
摘要翻译：根据一个实施例，应变和压力感测装置包括半导体电路单元和感测单元。半导体电路单元包括半导体衬底和晶体管。晶体管设置在半导体衬底上。感测单元设置在半导体电路单元上，并且具有空间和非空间部分。非空间部分与空间部分并置。感测单元还包括可移动光束，应变传感元件单元以及第一和第二掩埋互连。可移动光束具有固定和可移动部分，并且包括第一和第二互连层。固定部固定在非空间部。可动部分与晶体管分离，并从固定部分延伸到空间部分。应变传感元件单元固定在可动部上。第一和第二掩埋互连件设置在非空间部分中。

4. 发明申请

US20090078987A1 PROGRAMMABLE ELEMENT AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的可编程元件和制造方法
公开(公告)号：US20090078987A1
公开(公告)日：2009-03-26
申请号：US12143019
申请日：2008-06-20
申请人： Mariko Takayanagi
发明人： Mariko Takayanagi
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L21/823462 , H01L27/11568 , H01L29/792
摘要： In one aspect of the present invention, a programmable element, may include a semiconductor substrate, source/drain layers formed apart from each other in the upper surface of the semiconductor substrate, a gate insulating film including a charge-trapping film containing Hf and formed on a portion between the source/drain layers of the semiconductor substrate, and a gate electrode formed on the gate insulating film with a program voltage applied to the gate electrode.
摘要翻译：在本发明的一个方面中，可编程元件可以包括半导体衬底，在半导体衬底的上表面中彼此分开形成的源极/漏极层，栅极绝缘膜，其包括含有Hf的电荷捕获膜，并形成在半导体衬底的源极/漏极层之间的部分和形成在栅极绝缘膜上的栅电极，其中施加到栅电极的编程电压。

5. 发明授权

US07910970B2 Programmable element and manufacturing method of semiconductor device 有权
标题翻译：半导体器件的可编程元件和制造方法
公开(公告)号：US07910970B2
公开(公告)日：2011-03-22
申请号：US12143019
申请日：2008-06-20
申请人： Mariko Takayanagi
发明人： Mariko Takayanagi
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/28282 , H01L21/823462 , H01L27/11568 , H01L29/792
摘要： In one aspect of the present invention, a programmable element, may include a semiconductor substrate, source/drain layers formed apart from each other in the upper surface of the semiconductor substrate, a gate insulating film including a charge-trapping film containing Hf and formed on a portion between the source/drain layers of the semiconductor substrate, and a gate electrode formed on the gate insulating film with a program voltage applied to the gate electrode.
摘要翻译：在本发明的一个方面中，可编程元件可以包括半导体衬底，在半导体衬底的上表面中彼此分开形成的源极/漏极层，栅极绝缘膜，其包括含有Hf的电荷捕获膜，并形成在半导体衬底的源极/漏极层之间的部分和形成在栅极绝缘膜上的栅电极，其中施加到栅电极的编程电压。

6. 发明授权

US06675368B2 Apparatus for and method of preparing pattern data of electronic part 失效
标题翻译：电子部件图案数据的制作方法及方法
公开(公告)号：US06675368B2
公开(公告)日：2004-01-06
申请号：US09962454
申请日：2001-09-26
申请人： Mariko Takayanagi , Shunko Magoshi , Tatsuya Ohguro
发明人： Mariko Takayanagi , Shunko Magoshi , Tatsuya Ohguro
IPC分类号： G06F1750
CPC分类号： H01J37/3026 , H01J2237/31764 , Y10T428/24802
摘要： A method divides a layout area of an electronic part into sections, designs patterns according to circuit data of de electronic part, and draws the patterns in the layout area section by section so that the patterns in the sections may collectively form the electronic part. The method detects, among the patterns, any violation pattern that may cause a characteristic failure in the electronic part due to a section-to section connection error. Such violation pattern has a size L smaller than a threshold “k*La” where La is a section-to-section connection allowance and k is a coefficient. Also provided is an apparatus for executing the method.
摘要翻译：一种方法将电子部件的布局区域划分为部分，根据电子部件的电路数据设计图案，并逐段绘制布局区域中的图案，使得部分中的图案可以共同形成电子部件。该方法在模式之中检测到可能由于段到段连接错误而导致电子部件中的特征故障的任何违规模式。这种违反模式的尺寸L小于阈值“k * La”，其中La是截面连接容限，k是系数。还提供了一种用于执行该方法的装置。

7. 发明授权

US06545317B2 Semiconductor device having a gate electrode with a sidewall insulating film and manufacturing method thereof 失效
公开(公告)号：US06545317B2
公开(公告)日：2003-04-08
申请号：US09892574
申请日：2001-06-28
申请人： Akira Hokazono , Mariko Takayanagi
发明人： Akira Hokazono , Mariko Takayanagi
IPC分类号： H01L2976
CPC分类号： H01L29/66628 , H01L21/28052 , H01L21/28114 , H01L29/665 , H01L29/66545
摘要： A gate electrode is provided via a gate insulating film formed between the source and drain regions on a semiconductor substrate, wherein the sidewall of the gate electrode excluding the exposed part formed at the upper part thereof facing the source and drain regions is covered with a sidewall insulating film, and an epitaxial film is formed on the exposed part of the sidewall of the gate electrode but not formed on a top surface of the gate electrode. An element isolation region formed on the semiconductor substrate is composed of a first insulating film formed in the semiconductor substrate and a second insulating film which is formed inside the first insulating film and has a lower epitaxial growth rate than that of the first insulating film, and the surface of the source and drain regions is covered with a silicon layer, part of which runs onto the surface of the first insulating film.

8. 发明申请

US20110147839A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110147839A1
公开(公告)日：2011-06-23
申请号：US12640658
申请日：2009-12-17
申请人： Atsushi Yagishita , Makoto Fujiwara , Hirohisa Kawasaki , Mariko Takayanagi
发明人： Atsushi Yagishita , Makoto Fujiwara , Hirohisa Kawasaki , Mariko Takayanagi
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.
摘要翻译：提供多栅极金属氧化物硅晶体管和制造多栅极金属氧化物硅晶体管的方法。多栅极金属氧化物硅晶体管包含在浅沟槽区域之间包含一个或多个凸部的体硅衬底; 一个或多个在凸部上的电介质部分; 电介质部分上的一个或多个硅散热片; 在浅沟槽隔离区域的浅沟槽隔离层; 和栅电极。浅沟槽隔离层的上表面可以位于凸部的上表面下方，或者浅沟槽隔离层的上表面可以位于第一介电层的下表面和上表面之间。多栅极金属氧化物硅晶体管可以包含与源极/漏极区域中的凸部的侧表面相邻的第二间隔物。

9. 发明申请

US20070158705A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070158705A1
公开(公告)日：2007-07-12
申请号：US11619785
申请日：2007-01-04
申请人： Mariko Takayanagi
发明人： Mariko Takayanagi
IPC分类号： H01L29/76
CPC分类号： H01L29/4916 , H01L21/28035 , H01L21/2807 , H01L29/4966 , H01L29/517
摘要： A semiconductor device including a semiconductor substrate having at least one pair of a source region and a drain region being formed at a surface layer portion thereof, a gate insulating film being provided on a surface of the semiconductor substrate between the source region and the drain region and having a relative dielectric constant of 5 or more, and a gate electrode being provided on a surface of the gate insulating film and made of a polycrystalline silicon based material containing at least one type of impurity, wherein a substance which restricts movement of the impurity from the polycrystalline silicon based material to the gate insulating film is provided in a vicinity of an interface to the gate insulating film.
摘要翻译：一种半导体器件，包括在其表层部分形成有至少一对源极区和漏极区的半导体衬底，栅极绝缘膜设置在源极区和漏极区之间的半导体衬底的表面上并且具有5以上的相对介电常数，栅电极设置在所述栅极绝缘膜的表面上，并且由含有至少一种杂质的多晶硅基材料制成，其中限制所述杂质的移动的物质在与栅极绝缘膜的界面附近设置从多晶硅基材料到栅极绝缘膜。

10. 发明申请

US20050263803A1 Semiconductor device includes gate insulating film having a high dielectric constant 有权
公开(公告)号：US20050263803A1
公开(公告)日：2005-12-01
申请号：US11193349
申请日：2005-08-01
申请人： Mariko Takayanagi
发明人： Mariko Takayanagi
IPC分类号： H01L29/78 , C23C16/40 , C23C16/455 , H01L21/28 , H01L21/316 , H01L21/318 , H01L21/336 , H01L21/8234 , H01L29/423 , H01L29/51 , H01L29/76
CPC分类号： H01L21/823462 , C23C16/401 , C23C16/405 , C23C16/45525 , C23C16/45531 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/31608 , H01L21/31645 , H01L29/42364 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A semiconductor device comprising a semiconductor substrate and a MOSFET provided on the semiconductor substrate, the MOSFET including a gate insulating film and a gate electrode provided on the gate insulating film, wherein the gate insulating film has a higher dielectric constant in a side contacting the semiconductor substrate than in a side contacting the gate electrode.

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