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1. 发明授权

US08355469B2 Flexible timebase for eye diagram 有权
标题翻译：眼图的灵活时基
公开(公告)号：US08355469B2
公开(公告)日：2013-01-15
申请号：US13178803
申请日：2011-07-08
申请人： Daniel G. Baker , Barry A. McKibben , Michael D. Nakamura , Evan Albright , Scott E. Zink , Michael S. Overton
发明人： Daniel G. Baker , Barry A. McKibben , Michael D. Nakamura , Evan Albright , Scott E. Zink , Michael S. Overton
IPC分类号： H04L27/00 , H03K9/00
CPC分类号： H04L1/205 , G01R13/0254 , G01R31/31711 , G01R31/31725 , G01R31/31727
摘要： A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal, derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. A subtractor then subtracts the digital phase-locked loop feedback from the linear ramp to provide the input to the loop filter.
摘要翻译：眼图的灵活时基使用稳定的自由运行振荡器作为采样时钟，用于输入串行数字信号和从输入串行数字信号的细分恢复时钟导出的参考信号的等效时间采样。将参考信号样本提供给数字锁相环，其向眼图发生器提供灵活的时基。眼图发生器在对应于参考信号样本的时间累积输入的串行数字信号样本以产生眼图。数字锁相环中的线性相位检测器使用希尔伯特变换将参考信号样本转换为复信号，然后使用具有反正切查找表的CORDIC算法将其转换为相位值的线性斜坡。减法器然后从线性斜坡减去数字锁相环反馈，以将输入提供给环路滤波器。

2. 发明授权

US08184747B2 Flexible timebase for EYE diagram 有权
标题翻译： EYE图灵活时基
公开(公告)号：US08184747B2
公开(公告)日：2012-05-22
申请号：US11274687
申请日：2005-11-14
申请人： Daniel G. Baker , Barry A. McKibben , Michael D. Nakamura , Evan Albright , Scott E. Zink , Michael S. Overton
发明人： Daniel G. Baker , Barry A. McKibben , Michael D. Nakamura , Evan Albright , Scott E. Zink , Michael S. Overton
IPC分类号： H04L27/00 , H04B3/46
CPC分类号： H04L1/205 , G01R13/0254 , G01R31/31711 , G01R31/31725 , G01R31/31727
摘要： A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. The digital phase-locked loop feedback is subtracted from the linear ramp to provide the input to the loop filter.
摘要翻译：眼图的灵活时基使用稳定的自由运行振荡器作为采样时钟，用于输入串行数字信号的等效时间采样和从输入串行数字信号的细分恢复时钟导出的参考信号。将参考信号样本提供给数字锁相环，其向眼图发生器提供灵活的时基。眼图发生器在对应于参考信号样本的时间累积输入的串行数字信号样本以产生眼图。数字锁相环中的线性相位检测器使用希尔伯特变换将参考信号样本转换为复信号，然后使用具有反正切查找表的CORDIC算法将其转换为相位值的线性斜坡。从线性斜坡中减去数字锁相环反馈，为环路滤波器提供输入。

3. 发明授权

US07642822B2 Analog phase-locked loop 有权
标题翻译：模拟锁相环
公开(公告)号：US07642822B2
公开(公告)日：2010-01-05
申请号：US12061905
申请日：2008-04-03
申请人： Daniel G. Baker , Gilbert A. Hoffman , Michael S. Overton , Barry A. McKibben
发明人： Daniel G. Baker , Gilbert A. Hoffman , Michael S. Overton , Barry A. McKibben
IPC分类号： H03L7/06
CPC分类号： H03L7/093
摘要： Aspects of the present invention are related, in general, to Type-III phase-locked loops. In particular, aspects of the present invention relate to analog Type-III phase-locked loop arrangements comprising at least two signal paths, wherein each signal path may correspond to a bandwidth partition and may be selected by a selector according to a bandwidth parameter value. According to one aspect of the present invention, a first signal path may correspond to a fast loop (wide closed-loop bandwidth), and a second signal path may correspond to a slow loop (narrow closed-loop bandwidth).
摘要翻译：通常，本发明的方面涉及III型锁相环。具体地，本发明的方面涉及包括至少两个信号路径的模拟III型锁相环装置，其中每个信号路径可以对应于带宽分区，并且可以根据带宽参数值由选择器选择。根据本发明的一个方面，第一信号路径可以对应于快速环路（宽闭环带宽），并且第二信号路径可以对应于慢环路（窄闭环带宽）。

4. 发明授权

US09699446B2 Test and measurement device, system, and method for providing synchronized measurement views 有权
公开(公告)号：US09699446B2
公开(公告)日：2017-07-04
申请号：US12754583
申请日：2010-04-05
申请人： Xinyu Zhu , Barry A. McKibben , Laurent A. Melling, Jr. , Kevin T. Ivers , Michael S. Overton
发明人： Xinyu Zhu , Barry A. McKibben , Laurent A. Melling, Jr. , Kevin T. Ivers , Michael S. Overton
IPC分类号： H04N17/00
CPC分类号： H04N17/00
摘要： Embodiments of the invention include a test and measurement device, system, and method for synchronizing measurement views and configuration parameters across multiple input channels or devices. A method includes receiving signals under test associated with multiple input channels of the test and measurement instrument or with multiple devices, selecting a measurement view of one input signal or device, receiving a synchronized view enable preference from a user control interface, and synchronizing the measurement view or configuration parameters of the other signals or devices with what was chosen on the first signal or device. A test and measurement instrument includes input terminals to receive the input signals, a user control interface to receive input from an operator, a display to provide measurement information about the input signals, and a synchronization control unit to synchronize measurement views and/or configuration parameters between the inputs or devices.

5. 发明申请

US20090219395A1 Measurement and Display for Video Peak Jitter with Expected Probability 审中-公开
标题翻译：视频峰值抖动的测量和显示具有预期的概率
公开(公告)号：US20090219395A1
公开(公告)日：2009-09-03
申请号：US12065243
申请日：2006-08-28
申请人： Daniel G. Baker , Barry A. McKibben
发明人： Daniel G. Baker , Barry A. McKibben
IPC分类号： H04N17/00
CPC分类号： H04N17/00 , G01R31/31709
摘要： A system and method are provided to generate a histogram of jitter peak values within histogram hardware. The histogram is then transferred to a jitter analyzer, which is implemented in either dedicated hardware or software running on a general purpose processor. The jitter analyzer calculates a cumulative distribution function (CDF) array and a complementary cumulative distribution function (CCDF) array based upon the histogram, and determines the peak jitter values based upon a probability value.
摘要翻译：提供了一种系统和方法来生成直方图硬件中抖动峰值的直方图。然后将直方图传输到抖动分析器，抖动分析器以通用处理器上运行的专用硬件或软件实现。抖动分析器基于直方图计算累积分布函数（CDF）阵列和互补累积分布函数（CCDF）阵列，并且基于概率值确定峰值抖动值。

6. 发明授权

US4598234A Digital image correction circuit for cathode ray tube displays 失效
标题翻译：用于阴极射线管显示器的数字图像校正电路
公开(公告)号：US4598234A
公开(公告)日：1986-07-01
申请号：US614509
申请日：1984-05-29
申请人： Barry A. McKibben
发明人： Barry A. McKibben
IPC分类号： H04N5/68 , H04N3/26 , H01J29/56
CPC分类号： H04N3/26
摘要： A digital electron optics correction circuit for correcting the focus and astigmatism in a displayed image on a CRT is disclosed. The circuit includes a clock generator for generating a selected number of pulses between each horizontal blanking synchronization pulse. These clock pulses are then counted by an X-address counter and a first address signal is generated corresponding to a particular horizontal position on the CRT screen for each count of the X-address counter. A pulse generator circuit is also provided which is coupled to receive the vertical blanking synchronization pulses and which provides a selected number of output pulses for each vertical blanking synchronization pulse. A Y-address counter counts the output pulses from the pulse generator circuit and provides a second address signal corresponding to a particular vertical position on the CRT screen for each count. These X- and Y-addresses are then input to focus and astigmatism ROMS which are preprogrammed with an appropriate control correction signal for each X-Y-address. In a first embodiment of the invention, the pulse generator circuit inclues a dividing circuit which is coupled to receive the horizontal blanking synchronization pulses. The dividing circuit then provides an output pulse for every N2 pulses received, and each such output pulse is then utilized to increment the Y-address counter. In a second embodiment, the pulse generator circuit includes a second clock generator for generating N3 pulses between successive vertical blanking synchronization pulses, with each clock pulse being used to increment the Y-address counter. Also disclosed in a specialized clock generator cirucit for generating a preselected number of pulses between successive gating pulses.
摘要翻译：公开了一种用于校正CRT上的显示图像中的聚焦和散光的数字电子光学校正电路。电路包括时钟发生器，用于在每个水平消隐同步脉冲之间产生选定数量的脉冲。然后通过X地址计数器对这些时钟脉冲进行计数，并且针对X地址计数器的每个计数，对应于CRT屏幕上的特定水平位置产生第一地址信号。还提供脉冲发生器电路，其被耦合以接收垂直消隐同步脉冲，并且为每个垂直消隐同步脉冲提供选定数量的输出脉冲。 Y地址计数器对来自脉冲发生器电路的输出脉冲进行计数，并且针对每个计数提供对应于CRT屏幕上的特定垂直位置的第二地址信号。然后将这些X和Y地址输入到用于每个X-Y地址的适当的控制校正信号预编程的聚焦和散光ROMS。在本发明的第一实施例中，脉冲发生器电路包括一个分频电路，其被耦合以接收水平消隐同步脉冲。然后，分频电路为接收的每个N2脉冲提供输出脉冲，然后利用每个这样的输出脉冲来增加Y地址计数器。在第二实施例中，脉冲发生器电路包括用于在连续的垂直消隐同步脉冲之间产生N3个脉冲的第二时钟发生器，每个时钟脉冲用于递增Y地址计数器。还在专用时钟发生器cirucit中公开了用于在连续门控脉冲之间产生预选数量的脉冲。

7. 发明授权

US4554489A Resonant magnetic deflection circuit 失效
标题翻译：谐振磁偏转电路
公开(公告)号：US4554489A
公开(公告)日：1985-11-19
申请号：US449070
申请日：1982-12-13
申请人： Barry A. McKibben
发明人： Barry A. McKibben
IPC分类号： H04N3/16 , A61B5/00 , A61B5/021 , G09G1/04 , G09G1/16 , H03K4/62 , H03K4/64 , H04N3/227 , H01J29/70
CPC分类号： H03K4/64 , H03K4/62 , A61B5/0002 , A61B5/021
摘要： A resonant magnetic deflection circuit is disclosed for reducing a retrace period of an electron beam scanning within a cathode ray tube (CRT) apparatus. Opposite polarity flyback voltage pulses occur at both ends of a deflection coil. As a result, an effective retrace voltage appearing across the deflection coil is approximately doubled, thereby reducing the retrace period of the electron beam scanning within the CRT apparatus. One end of the deflection coil is connected to a reference level source through a first parallel circuit and an S-correction capacitor, the other end thereof being connected to the reference level source through a second parallel circuit. The first and second parallel circuits comprise switching devices, damper diodes and retrace capacitors. Moreover, both ends of the deflection coil are connected to a power supply through a flyback transformer.
摘要翻译：公开了一种用于减少阴极射线管（CRT）装置内的电子束扫描的回扫周期的共振磁偏转电路。偏转线圈的两端出现相反极性反激电压脉冲。结果，出现在偏转线圈两端的有效回扫电压近似加倍，从而减少CRT设备内电子束扫描的回扫周期。偏转线圈的一端通过第一并联电路和S校正电容器连接到参考电平源，其另一端通过第二并联电路连接到参考电平源。第一和第二并联电路包括开关器件，阻尼二极管和回扫电容器。此外，偏转线圈的两端通过反激式变压器与电源连接。

8. 发明授权

US4249112A Dynamic focus and astigmatism correction circuit 失效
标题翻译：动态聚焦和散光校正电路
公开(公告)号：US4249112A
公开(公告)日：1981-02-03
申请号：US76533
申请日：1979-09-18
申请人： Barry A. McKibben
发明人： Barry A. McKibben
IPC分类号： H01J29/56 , H01J29/58 , H04N3/26
CPC分类号： H04N3/26
摘要： A dynamic focus system for a cathode ray tube display system is described. In some cathode ray tubes an electrostatic or electromagnetic stigmator is driven by a correction signal derived from the beam deflection signals. The required signal is proportional to the product of the horizontal and vertical deflection signals. The described system incorporates a means for making the constant of proportionality independently adjustable for each quadrant of the cathode ray tube screen.
摘要翻译：描述了用于阴极射线管显示系统的动态聚焦系统。在一些阴极射线管中，通过从光束偏转信号导出的校正信号来驱动静电或电磁标枪。所需信号与水平和垂直偏转信号的乘积成比例。所描述的系统包括用于使阴极射线管屏幕的每个象限可独立调节比例常数的装置。

9. 发明授权

US5448589A Circuit for sensing cable effects for automatic equalization 失效
标题翻译：用于感应电缆效应的电路用于自动均衡
公开(公告)号：US5448589A
公开(公告)日：1995-09-05
申请号：US283413
申请日：1994-08-01
申请人： Barry A. McKibben
发明人： Barry A. McKibben
IPC分类号： H04B3/06 , H04B3/14
CPC分类号： H04B3/06
摘要： An automatic equalizer has a circuit for sensing cable effects that generates a control signal for a variable equalizer. A digital signal from a transmission channel is input to the variable equalizer to produce an equalized digital signal as a function of the control signal. The equalized digital signal is input to the sensing circuit which detects over-shoot or under-shoot of transitions in the equalized digital signal and adjusts the control signal accordingly to produce a balance in the transitions.
摘要翻译：自动均衡器具有用于感测产生用于可变均衡器的控制信号的电缆效应的电路。来自传输信道的数字信号被输入到可变均衡器，以产生作为控制信号的函数的均衡的数字信号。均衡的数字信号被输入到感测电路，其检测均衡的数字信号中的转换的过拍或欠拍，并相应地调整控制信号以在转换中产生平衡。

10. 发明授权

US4864167A Dual function peak metering circuit 失效
标题翻译：双功能峰值计量电路
公开(公告)号：US4864167A
公开(公告)日：1989-09-05
申请号：US227028
申请日：1988-08-01
申请人： Barry A. McKibben , Edward J. Cleary, Jr.
发明人： Barry A. McKibben , Edward J. Cleary, Jr.
IPC分类号： G01R19/04
CPC分类号： G01R19/04
摘要： A dual function peak metering circuit provides both monitoring and measuring functions for a composite signal having both modulated and unmodulated components. A full-wave rectified version of the composite signal is input to an envelope detector that drives a peak weighting circuit and a variable limiter. The output of the peak weighting circuit controls a threshold level for the variable limiter. The peaks of the signal at the output of the variable limiter are detected with an instantaneous peak-hold circuit that is periodically sampled and reset under microprocessor control. The microprocessor then displays the sampled value both graphically and numerically.
摘要翻译：双功能峰值计量电路为具有调制和未调制组件的复合信号提供监测和测量功能。将复合信号的全波整流版本输入到驱动峰值加权电路和可变限幅器的包络检测器。峰值加权电路的输出控制可变限幅器的阈值电平。在可变限制器的输出处的信号的峰值由在微处理器控制下周期性采样和复位的瞬时峰值保持电路来检测。然后微处理器以图形和数字方式显示采样值。

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