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1. 发明授权

US08184747B2 Flexible timebase for EYE diagram 有权
标题翻译： EYE图灵活时基
公开(公告)号：US08184747B2
公开(公告)日：2012-05-22
申请号：US11274687
申请日：2005-11-14
申请人： Daniel G. Baker , Barry A. McKibben , Michael D. Nakamura , Evan Albright , Scott E. Zink , Michael S. Overton
发明人： Daniel G. Baker , Barry A. McKibben , Michael D. Nakamura , Evan Albright , Scott E. Zink , Michael S. Overton
IPC分类号： H04L27/00 , H04B3/46
CPC分类号： H04L1/205 , G01R13/0254 , G01R31/31711 , G01R31/31725 , G01R31/31727
摘要： A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. The digital phase-locked loop feedback is subtracted from the linear ramp to provide the input to the loop filter.
摘要翻译：眼图的灵活时基使用稳定的自由运行振荡器作为采样时钟，用于输入串行数字信号的等效时间采样和从输入串行数字信号的细分恢复时钟导出的参考信号。将参考信号样本提供给数字锁相环，其向眼图发生器提供灵活的时基。眼图发生器在对应于参考信号样本的时间累积输入的串行数字信号样本以产生眼图。数字锁相环中的线性相位检测器使用希尔伯特变换将参考信号样本转换为复信号，然后使用具有反正切查找表的CORDIC算法将其转换为相位值的线性斜坡。从线性斜坡中减去数字锁相环反馈，为环路滤波器提供输入。

2. 发明授权

US08355469B2 Flexible timebase for eye diagram 有权
标题翻译：眼图的灵活时基
公开(公告)号：US08355469B2
公开(公告)日：2013-01-15
申请号：US13178803
申请日：2011-07-08
申请人： Daniel G. Baker , Barry A. McKibben , Michael D. Nakamura , Evan Albright , Scott E. Zink , Michael S. Overton
发明人： Daniel G. Baker , Barry A. McKibben , Michael D. Nakamura , Evan Albright , Scott E. Zink , Michael S. Overton
IPC分类号： H04L27/00 , H03K9/00
CPC分类号： H04L1/205 , G01R13/0254 , G01R31/31711 , G01R31/31725 , G01R31/31727
摘要： A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal, derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. A subtractor then subtracts the digital phase-locked loop feedback from the linear ramp to provide the input to the loop filter.
摘要翻译：眼图的灵活时基使用稳定的自由运行振荡器作为采样时钟，用于输入串行数字信号和从输入串行数字信号的细分恢复时钟导出的参考信号的等效时间采样。将参考信号样本提供给数字锁相环，其向眼图发生器提供灵活的时基。眼图发生器在对应于参考信号样本的时间累积输入的串行数字信号样本以产生眼图。数字锁相环中的线性相位检测器使用希尔伯特变换将参考信号样本转换为复信号，然后使用具有反正切查找表的CORDIC算法将其转换为相位值的线性斜坡。减法器然后从线性斜坡减去数字锁相环反馈，以将输入提供给环路滤波器。

3. 发明授权

US4516042A Clamp circuits 失效
标题翻译：钳位电路
公开(公告)号：US4516042A
公开(公告)日：1985-05-07
申请号：US393966
申请日：1982-06-30
申请人： Michael D. Nakamura
发明人： Michael D. Nakamura
IPC分类号： H04N5/18 , H04N5/213 , H03K5/08
CPC分类号： H04N5/185 , H04N5/213
摘要： A circuit for providing a signal which is clamped to a desired DC voltage level comprises an amplifier for receiving an input signal and a feedback loop for developing an offset signal for combination with the input signal by the amplifier to provide an output signal at the desired DC voltage level. The feedback loop includes a noise detector for detecting the level of noise present in the output signal, and adjusting the time constant of the feedback loop in dependence thereon.
摘要翻译：用于提供被钳位到期望的DC电压电平的信号的电路包括用于接收输入信号的放大器和用于开发偏移信号的反馈环路，用于与放大器的输入信号组合以提供期望DC的输出信号电压电平。反馈回路包括用于检测存在于输出信号中的噪声电平的噪声检测器，并根据其调整反馈回路的时间常数。

4. 发明授权

US5534939A Digital video clock generation system 失效
标题翻译：数字视频时钟发生系统
公开(公告)号：US5534939A
公开(公告)日：1996-07-09
申请号：US352641
申请日：1994-12-09
申请人： Michael D. Nakamura , Howard A. Landsman
发明人： Michael D. Nakamura , Howard A. Landsman
IPC分类号： H04N5/44 , H03L7/18 , H04N5/12 , H04N9/44 , H04N11/20 , H04N11/22 , H04N5/04
CPC分类号： H04N11/22 , H04N5/126 , H04N9/44 , H04N11/20
摘要： A digital clock generation system provides both a digital composite clock and a digital component clock synchronized with an input synchronization video signal. The digital composite clock is generated from the burst portion of the input synchronization video signal, and the digital component clock is synthesized from the digital composite clock. A frame timing pulse is generated at regular intervals from the composite sync of the input video signal for resetting the digital component clock to establish a defined phase relationship between the digital composite and component clocks according to an offset constant.
摘要翻译：数字时钟产生系统提供与输入同步视频信号同步的数字复合时钟和数字分量时钟。数字复合时钟由输入同步视频信号的脉冲串部分产生，数字分量时钟由数字复合时钟合成。根据输入视频信号的复合同步以规则的间隔产生帧定时脉冲，用于根据偏移常数复位数字分量时钟以建立数字复合和分量时钟之间的定义的相位关系。

5. 发明授权

US06696996B1 Method and apparatus to eliminate audible clicking transients when switching audio streams 有权
标题翻译：切换音频流时消除可听见的点击瞬变的方法和设备
公开(公告)号：US06696996B1
公开(公告)日：2004-02-24
申请号：US09544947
申请日：2000-04-07
申请人： Michael D. Nakamura , John C. Reynolds
发明人： Michael D. Nakamura , John C. Reynolds
IPC分类号： H03M900
CPC分类号： H04L12/66
摘要： A method and apparatus to switch between two audio streams without creating a clicking transient. A first serial audio stream is brought into a serial shift register. A series of samples of that audio stream are multiplied by reducing coefficients until a contribution of the first audio stream reaches zero. Then, a second serial audio stream is brought into the serial shift register. Increasing coefficients are applied to a series of samples until a contribution of the second audio stream is one.
摘要翻译：一种在两个音频流之间切换而不产生点击瞬变的方法和装置。第一串行音频流被带入串行移位寄存器。通过减少系数乘以该音频流的一系列样本，直到第一音频流的贡献达到零。然后，将第二串行音频流带入串行移位寄存器。将增加的系数应用于一系列样本，直到第二音频流的贡献为一。

6. 发明授权

US06545721B1 Video retiming through dynamic FIFO sizing 有权
标题翻译：通过动态FIFO大小调整视频重新定时
公开(公告)号：US06545721B1
公开(公告)日：2003-04-08
申请号：US09545392
申请日：2000-04-07
申请人： Michael D. Nakamura , John C. Reynolds
发明人： Michael D. Nakamura , John C. Reynolds
IPC分类号： H04N504
CPC分类号： H04N5/0736
摘要： A method and apparatus for retiming video. Vertical synchronization information (VSI) is detected in an incoming video stream. A VSI is also detected in both as output video stream and a reference video stream. Based on the difference between the VSI of the reference and output video stream reads or writes to a FIFO are suppressed until the VSI's are coincident.
摘要翻译：一种用于重新定时录像的方法和装置。在输入视频流中检测垂直同步信息（VSI）。 VSI也被检测为输出视频流和参考视频流。基于对FIFO的输出视频流的读取或写入之间的差异被抑制，直到VSI重合为止。

7. 发明授权

US4598315A Signal processing apparatus and method of operating such apparatus 失效
标题翻译：信号处理装置及其操作方法
公开(公告)号：US4598315A
公开(公告)日：1986-07-01
申请号：US476182
申请日：1983-03-17
申请人： Bruce J. Penney , Michael D. Nakamura
发明人： Bruce J. Penney , Michael D. Nakamura
IPC分类号： H04N5/073 , H04N5/14 , H04N5/268 , H04N17/00 , H04N5/04
CPC分类号： H04N17/00 , H04N5/0736
摘要： A signal processing apparatus comprises first and second switches connected respectively to an input terminal and an output terminal of the apparatus and defines first and second signal channels extending in parallel from the first switch to the second switch. The first and second switches are operable to connect a selected one of the signal channels between the input terminal and the output terminal. The first signal channel includes a signal processor, such as a frame synchronizer. The input terminal is connected to the signal processor even when the second channel is selected for connecting the input terminal to the output terminal so that a signal applied to the input terminal is applied to the signal processor as well as to the output terminal when the second channel is selected. Thus, the signal processor can be exercised and the output of the signal processor can be monitored while the second channel is utilized for transmitting a signal from the input terminal to the output terminal.
摘要翻译：信号处理装置包括分别连接到装置的输入端和输出端的第一和第二开关，并且限定从第一开关并行延伸到第二开关的第一和第二信号通道。第一和第二开关可操作以连接输入端和输出端之间的所选信号通道之一。第一信号通道包括信号处理器，诸如帧同步器。即使当选择第二通道将输入端子连接到输出端子时，输入端子连接到信号处理器，使得施加到输入端子的信号也被施加到信号处理器以及输出端子频道被选中。因此，可以利用信号处理器并且可以监视信号处理器的输出，同时利用第二通道将信号从输入端子发送到输出端子。

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