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1. 发明申请

US20180019781A1 SYSTEM AND METHOD FOR BUILT-IN SELF-TEST OF ELECTRONIC CIRCUITS 有权
公开(公告)号：US20180019781A1
公开(公告)日：2018-01-18
申请号：US15211782
申请日：2016-07-15
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： ROBERT FLOYD PAYNE , LAMBERT JACOB HELLEMAN
IPC分类号： H04B1/40 , G01R31/28 , H04B17/00 , H04L7/02
CPC分类号： H04B1/40 , G01R31/2884 , G01R31/3004 , G01R31/3016 , G01R31/31711 , H04B17/00 , H04L7/02
摘要： In described examples of a device with built-in-self-test, a multiplexer has at least first and second input terminals and is coupled to receive a first input signal at the first input terminal, a second input signal at the second input terminal, and selection signals. Also, the multiplexer is coupled to output: the first input signal in response to a first combination of the selection signals; the second input signal in response to a second combination of the selection signals; and an analog summation of the first and second input signals in response to a third combination of the selection signals.

2. 发明申请

US20160344577A1 DFE Margin Test Methods and Circuits that Decouple Sample feedback Timing 审中-公开
标题翻译： DFE边距测试方法和电路，可以将样本反馈时序分解
公开(公告)号：US20160344577A1
公开(公告)日：2016-11-24
申请号：US15165134
申请日：2016-05-26
申请人： Rambus Inc.
发明人： Brian S. Leibowitz , Bruno W. Garlepp
IPC分类号： H04L25/03 , H04L5/00 , H04J11/00
CPC分类号： H04L25/03057 , G01R31/31709 , G01R31/31711 , H04J11/0023 , H04L1/20 , H04L1/241 , H04L1/242 , H04L1/244 , H04L5/006 , H04L7/033 , H04L25/03146
摘要： Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.
摘要翻译：描述了数字接收机边缘测试的方法和电路。这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用于采用历史数据的接收机来减少符号间干扰（ISI）。一些实施例允许独立于采样定时来调整反馈定时以测量某些形式的相位未对准和抖动的影响。

3. 发明授权

US09116810B2 Margin test methods and circuits 有权
公开(公告)号：US09116810B2
公开(公告)日：2015-08-25
申请号：US14333665
申请日：2014-07-17
申请人： Rambus Inc.
发明人： Andrew Ho , Vladimir Stojanovic , Bruno W. Garlepp , Fred F. Chen
IPC分类号： G06F11/08 , G01R31/317 , H04L1/20 , H04L1/24 , H04L7/033 , H04B17/21 , H04L7/04 , H04L7/10 , H04L25/03
CPC分类号： H04B17/29 , G01R31/31711 , G06F11/08 , H04B17/21 , H04L1/20 , H04L1/241 , H04L1/242 , H04L7/033 , H04L7/043 , H04L7/10 , H04L25/03006 , H04L25/03057 , H04L25/03146 , H04L25/03949 , H04L27/01
摘要： Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

4. 发明申请

US20140266152A1 ON-CHIP EYE DIAGRAM CAPTURE 有权
标题翻译：片上眼图捕捉
公开(公告)号：US20140266152A1
公开(公告)日：2014-09-18
申请号：US13892334
申请日：2013-05-13
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Wen-Hung HUANG , Chien-Chun TSAI , Ying-Yu HSU
IPC分类号： G01R31/317
CPC分类号： G01R31/31708 , G01R31/31711
摘要： An eye diagram capture device includes a delay line arranged to receive a digital signal and output time delayed version of the digital signal. An edge detection circuit is arranged to receive the digital signal and the time delayed version of the digital signal, the edge detection circuit operating to output a signal corresponding to a logical value of the digital signal received coincident with an edge of the time delay version of the digital signal. A voltage comparator is arranged to receive the digital signal and a reference voltage. The voltage comparator operates to output a first signal when the a voltage of the digital signal and the reference voltage are equal to each other.
摘要翻译：眼图捕获装置包括布置成接收数字信号并输出数字信号的时间延迟版本的延迟线。边缘检测电路被布置为接收数字信号和数字信号的时间延迟版本，边缘检测电路操作以输出与所接收的数字信号的逻辑值相对应的信号，其与时间延迟版本数字信号。电压比较器布置成接收数字信号和参考电压。当数字信号的电压和参考电压彼此相等时，电压比较器操作以输出第一信号。

5. 发明授权

US08744012B1 On-chip eye viewer architecture for highspeed transceivers 有权
标题翻译：用于高速收发器的片上眼睛查看器架构
公开(公告)号：US08744012B1
公开(公告)日：2014-06-03
申请号：US13369108
申请日：2012-02-08
申请人： Weiqi Ding , Mingde Pan , Sergey Shumarayev , Peng Li
发明人： Weiqi Ding , Mingde Pan , Sergey Shumarayev , Peng Li
IPC分类号： H03K9/00
CPC分类号： H04L1/203 , G01R31/31711
摘要： System, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with a serial input signal either during or after equalization. The device may include an equalizer and eye viewer circuitry configured to select a node of the equalizer for eye monitoring of the input signal, which may be during or after equalization. In one embodiment, the eye viewer circuitry may provide a separate sampler for each respective node, while sharing a control logic and phase interpolator among the samplers. The eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the serial input signal, as seen from the selected node of the equalizer.
摘要翻译：提供了用于确定没有示波器的集成电路的串行输入信号的眼图的系统，方法和设备。例如，集成电路器件的一个实施例可能能够在均衡期间或之后确定与串行输入信号相关联的眼图。该装置可以包括均衡器和眼睛观察器电路，其被配置为选择均衡器的节点，用于在均衡期间或之后的输入信号的眼睛监视。在一个实施例中，眼睛观察器电路可以为每个相应节点提供单独的采样器，同时在采样器之间共享控制逻辑和相位插值器。从均衡器的选定节点看，眼睛观察器电路可以确定与串行输入信号相关联的眼图的水平和垂直边界。

6. 发明授权

US08625729B2 Method and device for clock data recovery 有权
标题翻译：时钟数据恢复的方法和设备
公开(公告)号：US08625729B2
公开(公告)日：2014-01-07
申请号：US12672482
申请日：2008-08-20
申请人： Ruben Villarino-Villa , Thomas Kuhwald , Markus Freidhof
发明人： Ruben Villarino-Villa , Thomas Kuhwald , Markus Freidhof
IPC分类号： H03D3/24
CPC分类号： H04L7/0083 , G01R31/31709 , G01R31/31711 , H03L7/06 , H04L1/205 , H04L7/0087 , H04L7/0331
摘要： A method for the recovery of a clock signal from a data signal, wherein the edges of the data signal and the clock signal are each presented by an ordered sequence of timing points, comprising determining missing edges in the sequence of data-signal edges, inserting new data-signal edges (Dx) into the sequence of data-signal edges to obtain a completed sequence of data-signal edges, and recovering the clock signal from the completed sequence of data-signal edges. The detection of missing edges in the sequence of data-signal edges is based on a prediction of the clock signal (FRONT CLOCK).
摘要翻译：一种用于从数据信号恢复时钟信号的方法，其中数据信号和时钟信号的边缘各自由定时点的有序序列呈现，包括确定数据信号边缘序列中的丢失边缘，插入将新的数据信号边缘（Dx）转换成数据信号边缘序列，以获得完整的数据信号边缘序列，以及从完成的数据信号边缘序列恢复时钟信号。在数据信号边缘序列中检测到丢失边缘是基于时钟信号（FRONT CLOCK）的预测。

7. 发明授权

US08559493B2 Margin test methods and circuits 有权
公开(公告)号：US08559493B2
公开(公告)日：2013-10-15
申请号：US12606159
申请日：2009-10-26
申请人： Andrew Ho , Vladimir Stojanovic , Bruno W. Garlepp , Fred F. Chen
发明人： Andrew Ho , Vladimir Stojanovic , Bruno W. Garlepp , Fred F. Chen
IPC分类号： H04B3/46 , H03K9/00
CPC分类号： H04B17/29 , G01R31/31711 , G06F11/08 , H04B17/21 , H04L1/20 , H04L1/241 , H04L1/242 , H04L7/033 , H04L7/043 , H04L7/10 , H04L25/03006 , H04L25/03057 , H04L25/03146 , H04L25/03949 , H04L27/01
摘要： Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

8. 发明授权

US08355469B2 Flexible timebase for eye diagram 有权
标题翻译：眼图的灵活时基
公开(公告)号：US08355469B2
公开(公告)日：2013-01-15
申请号：US13178803
申请日：2011-07-08
申请人： Daniel G. Baker , Barry A. McKibben , Michael D. Nakamura , Evan Albright , Scott E. Zink , Michael S. Overton
发明人： Daniel G. Baker , Barry A. McKibben , Michael D. Nakamura , Evan Albright , Scott E. Zink , Michael S. Overton
IPC分类号： H04L27/00 , H03K9/00
CPC分类号： H04L1/205 , G01R13/0254 , G01R31/31711 , G01R31/31725 , G01R31/31727
摘要： A flexible timebase for eye diagrams uses a stable free running oscillator as a sample clock for equivalent time sampling of an input serial digital signal and of a reference signal, derived from a subdivided recovered clock of the input serial digital signal. The reference signal samples are provided to a digital phase-locked loop that provides the flexible timebase to an eye pattern generator. The eye pattern generator accumulates the input serial digital signal samples at times corresponding to the reference signal samples to produce the eye diagram. A linear phase detector in the digital phase locked loop converts the reference signal samples to a complex signal using a Hilbert transform and then to a linear ramp of phase values using a CORDIC algorithm with arctangent lookup table. A subtractor then subtracts the digital phase-locked loop feedback from the linear ramp to provide the input to the loop filter.
摘要翻译：眼图的灵活时基使用稳定的自由运行振荡器作为采样时钟，用于输入串行数字信号和从输入串行数字信号的细分恢复时钟导出的参考信号的等效时间采样。将参考信号样本提供给数字锁相环，其向眼图发生器提供灵活的时基。眼图发生器在对应于参考信号样本的时间累积输入的串行数字信号样本以产生眼图。数字锁相环中的线性相位检测器使用希尔伯特变换将参考信号样本转换为复信号，然后使用具有反正切查找表的CORDIC算法将其转换为相位值的线性斜坡。减法器然后从线性斜坡减去数字锁相环反馈，以将输入提供给环路滤波器。

9. 发明授权

US07945406B2 Measuring device and method for measuring relative phase shifts of digital signals 有权
标题翻译：用于测量数字信号相对相移的测量装置和方法
公开(公告)号：US07945406B2
公开(公告)日：2011-05-17
申请号：US11530257
申请日：2006-09-08
申请人： Stephane Kirmser , Heinz Mattes , Sebastian Sattler
发明人： Stephane Kirmser , Heinz Mattes , Sebastian Sattler
IPC分类号： G01R25/00 , G01R29/26
CPC分类号： G01R31/31711 , G01R25/00 , G01R31/31725
摘要： M periods of the test signal and of the reference signal are received. The periods of the test signal and of the reference signal are in each case Tsig long. The test signal is sampled with N sampled values at a sampling frequency fs=1/Ts. Also, N*Ts=M*Tsig, where N>M. The sampled values are numbered progressively by n, for which 0≦n ≦N−1. The sampled values have a defined relative phase shift with respect to the reference signal. The phase shift Tφ is calculated by ∑ i = 0 M - 1 ⁢ ⁢ Idx ⁡ ( i ) + K , K being a constant and Idx(i) corresponding to the number n which is either the first sampled value after a test signal zero crossing during the reference signal's ith period or the last sampled value before a test signal zero crossing during the reference signal's ith period. Either only rising or only falling zero crossings are taken into account.
摘要翻译：接收测试信号和参考信号的M个周期。测试信号和参考信号的周期在每种情况下都是长度。以采样频率fs = 1 / Ts的N个采样值对测试信号进行采样。另外，N * Ts = M * Tsig，其中N> M。采样值逐渐被n编号，其中0＆nlE; n＆nlE; N-1。采样值相对于参考信号具有限定的相对相移。相移T＆phgr 通过Σi = 0 M -1优先Idx⁡（i）+ K，K是常数，Idx（i）对应于在参考期间测试信号过零之后的第一采样值的数量n 在参考信号第i个周期之前，测试信号过零之前的信号第i个周期或最后一个采样值。只考虑上升或下降的零交叉点。

10. 发明申请

US20100074314A1 Margin Test Methods And Circuits 有权
标题翻译：保证金测试方法和电路
公开(公告)号：US20100074314A1
公开(公告)日：2010-03-25
申请号：US12606159
申请日：2009-10-26
申请人： Vladimir Stojanovic , Andrew Ho , Bruno W. Garlepp , Fred F. Chen
发明人： Vladimir Stojanovic , Andrew Ho , Bruno W. Garlepp , Fred F. Chen
IPC分类号： H04B17/00 , H04B1/10 , G06F11/00
CPC分类号： H04B17/29 , G01R31/31711 , G06F11/08 , H04B17/21 , H04L1/20 , H04L1/241 , H04L1/242 , H04L7/033 , H04L7/043 , H04L7/10 , H04L25/03006 , H04L25/03057 , H04L25/03146 , H04L25/03949 , H04L27/01
摘要： Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.
摘要翻译：描述了数字接收机边缘测试的方法和电路。这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用于采用历史数据的接收机来减少符号间干扰（ISI）。一些实施例检测未知模式的输入数据流的接收错误，因此可以用于系统内边缘测试。这样的系统可以适于在设备操作期间动态地改变系统参数，以保持足够的余量，尽管由于例如系统噪声环境的波动。温度和电源电压变化。还描述了绘制和解释由所公开的方法和电路产生的滤波和未滤波的误差数据的方法。一些实施例可以过滤错误数据以促进模式特定的边缘测试。

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