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1. 发明授权

US5493520A Two state leading zero/one anticipator (LZA) 失效
标题翻译：两个国家领先的零/一预期者（LZA）
公开(公告)号：US5493520A
公开(公告)日：1996-02-20
申请号：US228323
申请日：1994-04-15
申请人： Martin S. Schmookler , Donald G. Mikan, Jr.
发明人： Martin S. Schmookler , Donald G. Mikan, Jr.
IPC分类号： G06F7/483 , G06F7/50 , G06F7/74 , G06F7/00
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49936
摘要： An apparatus and method for anticipating leading zeros/ones used in normalizing the results of a full adder. The propagate (P), generate (G) and zero (Z) states of the two inputs to the adder are combined in two stages of logic to derive a pair of state outputs L.phi.S and L1S which fully specify by respective bit strings the leading zero and leading one conditions of the output from the adder. The two state bit strings, one representing the leading zero evaluation and the second representing the leading one evaluation, are then compared to determine which one of the two is applicable, correspondingly indicating whether the adder result is a positive or a negative value, and the number of leading bit positions requiring shifted removal during the normalization process. The leading 0/1 anticipator according to the present invention lends itself to high speed and low device count circuit implementations.
摘要翻译：一种用于预测用于对全加器结果进行归一化的前导零的装置和方法。将加法器的两个输入的传播（P），生成（G）和零（Z）状态组合在逻辑的两个阶段以导出由各个位串完全指定的一对状态输出L phi S和L1S 前导零和前导条件的输出从加法器。然后比较两个状态位串，一个代表前导零评估，第二个表示前导评估，然后比较两个状态位串中哪一个是否适用，相应地指示加法器结果是正值还是负值，在标准化过程中需要移位的前导位位置数。根据本发明的领先0/1预测器适用于高速和低器件数电路实现。

2. 发明授权

US08502564B2 Adjustable Schmitt trigger 有权
标题翻译：可调施密特触发器
公开(公告)号：US08502564B2
公开(公告)日：2013-08-06
申请号：US13192690
申请日：2011-07-28
申请人： Donald G. Mikan, Jr.
发明人： Donald G. Mikan, Jr.
IPC分类号： H03K19/20 , H03K19/094
CPC分类号： H03K3/3565
摘要： A circuit comprises an inverter, a first transistor, a second transistor, and at least one switching circuit. The inverter has a first node and a second node. The first transistor has a first terminal, a second terminal, and a third terminal. The second transistor has a fourth terminal, a fifth terminal, and a sixth terminal. The at least one switching circuit is configured to switch a connection of at least one of the first transistor and the second transistor to the inverter. The second terminal and the fifth terminal are coupled to the first node. The third terminal and the sixth terminal are coupled to the second node. The first transistor and the second transistor are configured to cause a plurality of time delays at the second node.
摘要翻译：电路包括反相器，第一晶体管，第二晶体管和至少一个开关电路。逆变器具有第一节点和第二节点。第一晶体管具有第一端子，第二端子和第三端子。第二晶体管具有第四端子，第五端子和第六端子。至少一个开关电路被配置为将第一晶体管和第二晶体管中的至少一个的连接切换到逆变器。第二终端和第五终端耦合到第一节点。第三终端和第六终端耦合到第二节点。第一晶体管和第二晶体管被配置为在第二节点处引起多个时间延迟。

3. 发明授权

US5764549A Fast floating point result alignment apparatus 失效
标题翻译：快速浮点结果对齐装置
公开(公告)号：US5764549A
公开(公告)日：1998-06-09
申请号：US639573
申请日：1996-04-29
申请人： Andrew A. Bjorksten , Donald G. Mikan, Jr. , Martin S. Schmookler
发明人： Andrew A. Bjorksten , Donald G. Mikan, Jr. , Martin S. Schmookler
IPC分类号： G06F5/01
CPC分类号： G06F5/012
摘要： A device for aligning the radix point of an unaligned binary result of a floating point operation to a normalized or denormalized position is provided. The device comprises an alignment circuit that produces a shift alignment vector indicating the position of the most significant bit of the unaligned result that is set, when a normalized result is required, and that produces a shift alignment vector indicating the position of a bit of the unaligned result having the weight of a minimum allowable exponent for a given format, when a denormalized result is required. A shift register responsive to the alignment circuit shifts the unaligned result by the number of bits indicated by the shift alignment vector. The bit of the unaligned result having the weight of the minimum allowable exponent for the given format is determined by subtracting the binary value of the minimum allowable exponent from the binary value of the most significant bit of the unaligned result, wherein the difference indicates the number of bits from the most significant bit that the bit having the weight of the minimum allowable exponent is positioned.
摘要翻译：提供了用于将浮点运算的未对齐二进制结果的基数与归一化或非归一化位置对准的装置。该装置包括对准电路，当需要归一化结果时，该对准电路产生指示所设置的未对准结果的最高有效位的位置的移位对准矢量，并且产生一个移位对齐矢量，其指示位当需要非规范化结果时，对于给定格式，具有最小可允许指数权重的未对齐结果。响应于对准电路的移位寄存器将未对齐结果移位由移位对准矢量指示的位数。通过从未对齐结果的最高有效位的二进制值中减去最小可允许指数的二进制值来确定具有给定格式的最小允许指数权重的未对齐结果的位，其中该差表示数字来自最高有效位的位具有最小允许指数的权重的位被定位。

4. 发明授权

US5636156A Adder with improved carry lookahead structure 失效
标题翻译：加法器具有改进的进位先行结构
公开(公告)号：US5636156A
公开(公告)日：1997-06-03
申请号：US730166
申请日：1996-10-15
申请人： Donald G. Mikan, Jr. , Martin S. Schmookler
发明人： Donald G. Mikan, Jr. , Martin S. Schmookler
IPC分类号： G06F7/50 , G06F7/508
CPC分类号： G06F7/508 , G06F2207/3836 , G06F2207/5063
摘要： An adder circuit is disclosed having an improved carry lookahead arrangement. The number of carry lookahead stages required is log n, where n is equal to the number of bits in the adder. This arrangement has fanout limit based on the number of sets of propagate and generate signals which can be combined at each bit location of each stage. For example, if two-way merge circuits are used to combine two sets of signals together, then the maximum fanout from the previous stage would be limited to two (2). If four-way merge circuits were used, then the fanout would be limited to four (4). This low fanout is achieved without increasing the number of stages by overlapping the groups that are combined in each step.
摘要翻译：公开了一种具有改进的进位前视装置的加法器电路。所需的进位前视级数是log n，其中n等于加法器中的位数。这种布置具有基于传播集合的数量的扇出限制，并且可以在每个阶段的每个比特位置处产生可以组合的信号。例如，如果使用双向合并电路将两组信号组合在一起，则来自前一级的最大扇出输出将被限制为两（2）。如果使用四路合并电路，则扇出将限制为四（4）。通过重叠在每个步骤中组合的组来实现这种低扇出，而不增加级数。

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