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    • 1. 发明授权
      US08103898B2 Explicit skew interface for mitigating crosstalk and simultaneous switching noise 有权
    • Explicit skew interface for mitigating crosstalk and simultaneous switching noise
    • 用于减轻串扰和同时开关噪声的显式偏移接口
    • US08103898B2
    • 2012-01-24
    • US11969801
    • 2008-01-04
    • Dragos Dimitriu , Timothy Hollis
    • Dragos Dimitriu , Timothy Hollis
    • G06F1/00 , H04J1/12 , H04J3/10
    • H04L7/04 , G06F13/4072 , Y02D10/14 , Y02D10/151
    • Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise.
    • 公开了诸如涉及被配置为接收和处理电子数据的芯片间接口的方法和装置。 一个这样的接口包括接收机电路，其包括配置成在时钟树输入处接收时钟信号的时钟树。 时钟树分配从时钟信号延迟的多个时钟信号，使得一个或多个时钟信号具有与其它时钟信号的延迟不同的延迟。 接收机电路还包括多个数据输入锁存器，其被配置为在两个或多个不同的时间点上接收多个数据元素。 该配置至少部分地减少串扰和同时切换输出噪声。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明申请
      US20090174455A1 EXPLICIT SKEW INTERFACE FOR MITIGATING CROSSTALK AND SIMULTANEOUS SWITCHING NOISE 有权
    • EXPLICIT SKEW INTERFACE FOR MITIGATING CROSSTALK AND SIMULTANEOUS SWITCHING NOISE
    • 用于减轻搅拌机和同时切换噪音的显示切割界面
    • US20090174455A1
    • 2009-07-09
    • US11969801
    • 2008-01-04
    • Dragos Dimitriu , Timothy Hollis
    • Dragos Dimitriu , Timothy Hollis
    • G06F1/04
    • H04L7/04 , G06F13/4072 , Y02D10/14 , Y02D10/151
    • Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise.
    • 公开了诸如涉及被配置为接收和处理电子数据的芯片间接口的方法和装置。 一个这样的接口包括接收机电路，其包括配置成在时钟树输入处接收时钟信号的时钟树。 时钟树分配从时钟信号延迟的多个时钟信号，使得一个或多个时钟信号具有与其它时钟信号的延迟不同的延迟。 接收机电路还包括多个数据输入锁存器，其被配置为在两个或多个不同的时间点上接收多个数据元素。 该配置至少部分地减少串扰和同时切换输出噪声。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US08341452B2 Explicit skew interface for reducing crosstalk and simultaneous switching noise 有权
    • Explicit skew interface for reducing crosstalk and simultaneous switching noise
    • 显式偏移接口，用于减少串扰和同时开关噪声
    • US08341452B2
    • 2012-12-25
    • US13353603
    • 2012-01-19
    • Dragos Dimitriu , Timothy Hollis
    • Dragos Dimitriu , Timothy Hollis
    • G06F1/00 , H04J1/12 , H04J3/10
    • H04L7/04 , G06F13/4072 , Y02D10/14 , Y02D10/151
    • Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise.
    • 公开了诸如涉及被配置为接收和处理电子数据的芯片间接口的方法和装置。 一个这样的接口包括接收机电路，其包括配置成在时钟树输入处接收时钟信号的时钟树。 时钟树分配从时钟信号延迟的多个时钟信号，使得一个或多个时钟信号具有与其它时钟信号的延迟不同的延迟。 接收机电路还包括多个数据输入锁存器，其被配置为在两个或多个不同的时间点上接收多个数据元素。 该配置至少部分地减少串扰和同时切换输出噪声。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明申请
      US20120114087A1 EXPLICIT SKEW INTERFACE FOR REDUCING CROSSTALK AND SIMULTANEOUS SWITCHING NOISE 有权
    • EXPLICIT SKEW INTERFACE FOR REDUCING CROSSTALK AND SIMULTANEOUS SWITCHING NOISE
    • 用于减少摇滚音箱和同时开关噪音的显示切口界面
    • US20120114087A1
    • 2012-05-10
    • US13353603
    • 2012-01-19
    • Dragos Dimitriu , Timothy Hollis
    • Dragos Dimitriu , Timothy Hollis
    • H04L7/04
    • H04L7/04 , G06F13/4072 , Y02D10/14 , Y02D10/151
    • Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise.
    • 公开了诸如涉及被配置为接收和处理电子数据的芯片间接口的方法和装置。 一个这样的接口包括接收机电路，其包括配置成在时钟树输入处接收时钟信号的时钟树。 时钟树分配从时钟信号延迟的多个时钟信号，使得一个或多个时钟信号具有与其它时钟信号的延迟不同的延迟。 接收机电路还包括多个数据输入锁存器，其被配置为在两个或多个不同的时间点上接收多个数据元素。 该配置至少部分地减少串扰和同时切换输出噪声。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US07425847B2 Input buffer with optimal biasing and method thereof 有权
    • Input buffer with optimal biasing and method thereof
    • 具有最佳偏置的输入缓冲器及其方法
    • US07425847B2
    • 2008-09-16
    • US11347477
    • 2006-02-03
    • Dragos Dimitriu
    • Dragos Dimitriu
    • H03K19/094 , H03K19/0175
    • H03K19/018528
    • A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals. The input buffer further includes a second stage coupled to the differential internal signals and configured to generate differential output signals. A memory device includes a memory array with the respective input buffer. Differential input signals are received and differential internal signals are generated as biased in response to an averaging of the differential internal signals. Differential output signals are generated in a second stage from the differential internal signals.
    • 描述偏置输入缓冲器的方法和电路以使输出信号的质量最大化。 输入缓冲器包括第一级，用于接收差分输入信号并产生响应于差分内部信号的平均而偏置的差分内部信号。 输入缓冲器还包括耦合到差分内部信号并被配置为产生差分输出信号的第二级。 存储器件包括具有相应输入缓冲器的存储器阵列。 接收差分输入信号，并且响应于差分内部信号的平均而产生偏置的差分内部信号。 差分输出信号在差分内部信号的第二级产生。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 8. 发明申请
      US20100231300A1 INPUT BUFFER WITH OPTIMAL BIASING AND METHOD THEREOF 有权
    • INPUT BUFFER WITH OPTIMAL BIASING AND METHOD THEREOF
    • 输入缓冲器具有最佳偏移及其方法
    • US20100231300A1
    • 2010-09-16
    • US12787131
    • 2010-05-25
    • Dragos Dimitriu
    • Dragos Dimitriu
    • H03F3/45
    • H03K19/018528
    • A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals. The input buffer further includes a second stage coupled to the differential internal signals and configured to generate differential output signals. A memory device includes a memory array with the respective input buffer. Differential input signals are received and differential internal signals are generated as biased in response to an averaging of the differential internal signals. Differential output signals are generated in a second stage from the differential internal signals.
    • 描述偏置输入缓冲器的方法和电路以使输出信号的质量最大化。 输入缓冲器包括第一级，用于接收差分输入信号并产生响应于差分内部信号的平均而偏置的差分内部信号。 输入缓冲器还包括耦合到差分内部信号并被配置为产生差分输出信号的第二级。 存储器件包括具有相应输入缓冲器的存储器阵列。 接收差分输入信号，并且响应于差分内部信号的平均而产生偏置的差分内部信号。 差分输出信号在差分内部信号的第二级产生。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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