专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09898625B2 Method and apparatus for limiting access to an integrated circuit (IC) 有权
公开(公告)号：US09898625B2
公开(公告)日：2018-02-20
申请号：US14727299
申请日：2015-06-01
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Alfredo Olmos , James R. Feddeler , Miten H. Nagda , Stefano Pietri
IPC分类号： G01R11/24 , G06F21/81 , G06F1/28 , G06F1/14 , G01R31/317
CPC分类号： G06F21/81 , G01R31/31719 , G06F1/14 , G06F1/28
摘要： A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.

2. 发明授权

US09891277B2 Secure low voltage testing 有权
公开(公告)号：US09891277B2
公开(公告)日：2018-02-13
申请号：US14502406
申请日：2014-09-30
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Joel R. Knight , James B. Eifert , Stefano Pietri , Steven K. Watkins
IPC分类号： G01R31/28 , G01R31/317
CPC分类号： G01R31/31719 , G01R31/31701
摘要： An integrated circuit includes a normal voltage detector configured to detect a normal voltage at which the integrated circuit being fully functional. A first voltage detector detects a first voltage that is less than the normal voltage. A second voltage detector detects a second voltage that is less than the first voltage. A reset module is coupled to a supply voltage, the normal voltage detector, the first voltage detector, and the second voltage detector. The reset module includes test logic to, when the supply voltage rises to the first voltage from the second voltage, perform a pass/fail test when the integrated circuit is in a pass/fail test mode, and perform a power up reset when the integrated circuit in not in the pass/fail test mode.

3. 发明授权

US09897649B2 Method for testing comparator and device therefor 有权
公开(公告)号：US09897649B2
公开(公告)日：2018-02-20
申请号：US14853090
申请日：2015-09-14
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Juxiang Ren , Chris C. Dao , Stefano Pietri
IPC分类号： G01R33/02 , H03K5/153 , G01R31/317 , G01R35/00 , G01R31/3163 , H03K5/24 , G01R31/3167
CPC分类号： G01R31/31703 , G01R31/3163 , G01R31/3167 , G01R35/00 , H03K5/24
摘要： An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.

4. 发明授权

US09584118B1 Substrate bias circuit and method for biasing a substrate 有权
标题翻译：衬底偏置电路和偏置衬底的方法
公开(公告)号：US09584118B1
公开(公告)日：2017-02-28
申请号：US14836223
申请日：2015-08-26
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Chris C. Dao , Stefano Pietri , Juxiang Ren , Robert S. Ruth
IPC分类号： H03K17/687
CPC分类号： H03K19/00315 , G05F3/205 , G11C5/146 , G11C11/4074 , G11C11/417 , H01L27/11582 , H01L28/00 , H03K19/018514 , H03K2217/0018
摘要： A substrate bias circuit and method for biasing a substrate are provided. A substrate bias circuit includes a first voltage source, a second voltage source, a diode coupled between the first voltage source and the second voltage source, and a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal. In one example, the first voltage source supplies, via the diode, the substrate terminal of a first transistor of the plurality of transistors during a power-up, and the second voltage source supplies the substrate terminal of the first transistor after the power-up.
摘要翻译：提供了一种用于偏置衬底的衬底偏置电路和方法。衬底偏置电路包括第一电压源，第二电压源，耦合在第一电压源和第二电压源之间的二极管以及多个晶体管，多个晶体管中的每个晶体管具有衬底端子。在一个示例中，第一电压源在上电期间通过二极管提供多个晶体管的第一晶体管的衬底端子，并且第二电压源在上电之后提供第一晶体管的衬底端子。

5. 发明授权

US09444405B1 Methods and structures for dynamically reducing DC offset 有权
标题翻译：动态降低直流偏移的方法和结构
公开(公告)号：US09444405B1
公开(公告)日：2016-09-13
申请号：US14864607
申请日：2015-09-24
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Chris C. Dao , Stefano Pietri
IPC分类号： H03M1/10 , H03F1/02 , H03F3/45 , H03F1/30
CPC分类号： H03F1/0205 , H03F3/45197 , H03F3/45771 , H03F2203/45038 , H03M1/765
摘要： An amplifier system includes a low offset amplifier having a first signal input, a second signal input, an output, a resistive digital to analog converter (RDAC) coupled between a first amplifying terminal and a second amplifying terminal of the amplifier that provides offset control, and a current supply coupled to the RDAC. The amplifier system further includes a low offset amplifier having a first signal input, a second signal input, an output, a resistive digital to analog converter coupled between a first amplifying terminal and a second amplifying terminal of the amplifier that provides offset control, and a current supply coupled to the RDAC. The amplifier system also further includes a load coupled to the output and to the second input of the amplifier and a controller coupled to the RDAC that provides an offset control of the first and second inputs by controlling the RDAC.
摘要翻译：放大器系统包括：具有第一信号输入的低偏移放大器，耦合在放大器的第一放大端和第二放大端之间的电阻数模转换器（RDAC）的第二信号输入端，以及与RDAC相连的电流供应。所述放大器系统还包括具有第一信号输入的低失调放大器，耦合在所述放大器的第一放大端与提供偏移控制的第二放大端之间的第二信号输入，输出，电阻数模转换器，以及目前的供应与RDAC相结合。放大器系统还进一步包括耦合到放大器的输出端和第二输入端的负载以及耦合到RDAC的控制器，RDAC通过控制RDAC来提供第一和第二输入的偏移控制。

6. 发明授权

US08710906B1 Fine grain voltage scaling of back biasing 有权
标题翻译：反向偏压的细晶粒电压缩放
公开(公告)号：US08710906B1
公开(公告)日：2014-04-29
申请号：US13764946
申请日：2013-02-12
申请人： Freescale Semiconductor, Inc.
发明人： Anis M. Jarrar , Stefano Pietri , Steven K. Watkins
IPC分类号： H03K3/01
CPC分类号： H01L21/761 , H01L21/823878 , H01L21/823892 , H01L27/0207
摘要： An integrated circuit including a substrate, multiple devices, and voltage control devices. The devices may include high threshold, low threshold, and standard threshold voltage devices. The devices and the voltage control devices are distributed across and coupled to the same substrate. Each voltage control device is configured to apply a back bias voltage at one of multiple discrete offset voltage levels. At least one voltage control device applies a first offset voltage level for back biasing high threshold voltage devices and at least one voltage control device applies a second offset voltage level for back biasing low threshold voltage devices. The selection of back biasing is based on relative population density of the different types of devices and varies across the substrate. Fine grain reverse back biasing reduces leakage current while reducing any performance decrease. Fine grain forward back biasing improves performance while reducing any leakage current increase.
摘要翻译：一种集成电路，包括基板，多个器件和电压控制器件。器件可以包括高阈值，低阈值和标准阈值电压器件。器件和电压控制器件分布在同一衬底上并耦合到同一衬底。每个电压控制装置被配置为以多个离散偏移电压电平之一施加反向偏置电压。至少一个电压控制装置施加用于后偏置高阈值电压装置的第一偏移电压电平，并且至少一个电压控制装置施加用于反向偏置低阈值电压装置的第二偏移电压电平。背偏置的选择是基于不同类型装置的相对总体密度，并且在基底之间变化。精细反向反向偏压降低漏电流，同时降低任何性能下降。精细的前馈偏置提高性能，同时减少任何漏电流增加。

7. 发明授权

US09697065B1 Systems and methods for managing reset 有权
公开(公告)号：US09697065B1
公开(公告)日：2017-07-04
申请号：US15064641
申请日：2016-03-09
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Kumar Abhishek , Steven K. Watkins , Garima Sharda , James M. Giandelone , Stefano Pietri , Thomas H. Luedeke
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0757 , G06F11/0745 , G06F11/22 , G06F13/00
摘要： A method for managing a reset process in a processing system is provided. The method includes enabling a watch dog unit based on a power-on reset (POR) event. A stuck in reset condition indication is received at the watch dog unit and used to determine whether the received reset condition indication corresponds to an unintentional reset condition. If the received reset condition indication is an indication of an unintentional reset condition, a watch dog POR trigger signal is generated and a reset state machine is repeated for system recovery.

8. 发明授权

US09285813B2 Supply voltage regulation with temperature scaling 有权
标题翻译：电源电压调节，温度调节
公开(公告)号：US09285813B2
公开(公告)日：2016-03-15
申请号：US14282527
申请日：2014-05-20
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Stefano Pietri , Juxiang Ren , Chris C. Dao , Anis M. Jarrar
IPC分类号： H01L35/00 , G05F1/575 , G05F1/46
CPC分类号： G05F1/575 , G05F1/463
摘要： A supply voltage regulation system for an IC including a temperature sensor that detects temperature of the IC, a scaling resistor coupled between a power grid and a feedback node of the IC, a regulator amplifier that compares a voltage of the feedback node with a reference voltage for developing a supply voltage for the IC, and a temperature scaling circuit that drives a scaling current to the scaling resistor via the feedback node to adjust the supply voltage based on temperature. The temperature scaling circuit may include one or more comparators that compare a temperature signal with corresponding temperature thresholds for selectively applying one or more bias currents to the scaling resistor. The scaling resistor may be coupled to a hot point of the power grid. A voltage difference between a hot point of a ground grid may be converted to a bias current applied to the scaling resistor.
摘要翻译：一种用于IC的电源电压调节系统，包括检测IC的温度的温度传感器，耦合在电网和IC的反馈节点之间的缩放电阻器，将反馈节点的电压与参考电压用于开发用于IC的电源电压，以及温度调节电路，其通过反馈节点驱动缩放电流到缩放电阻器，以基于温度调节电源电压。温度调节电路可以包括一个或多个比较器，其将温度信号与对应的温度阈值进行比较，以选择性地将一个或多个偏置电流施加到缩放电阻器。缩放电阻器可以耦合到电网的热点。接地电网的热点之间的电压差可以转换为施加到比例电阻器的偏置电流。

9. 发明申请

US20160003908A1 METHOD FOR TESTING COMPARATOR AND DEVICE THEREFOR 有权
公开(公告)号：US20160003908A1
公开(公告)日：2016-01-07
申请号：US14853090
申请日：2015-09-14
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Juxiang Ren , Chris C. Dao , Stefano Pietri
IPC分类号： G01R31/317 , H03K5/24
CPC分类号： G01R31/31703 , G01R31/3163 , G01R31/3167 , G01R35/00 , H03K5/24
摘要： An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.

10. 发明申请

US20150317496A1 METHOD AND APPARATUS FOR LIMITING ACCESS TO AN INTEGRATED CIRCUIT (IC) 有权
标题翻译：限制访问集成电路（IC）的方法和装置
公开(公告)号：US20150317496A1
公开(公告)日：2015-11-05
申请号：US14727299
申请日：2015-06-01
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Alfredo Olmos , James R. Feddeler , Miten H. Nagda , Stefano Pietri
IPC分类号： G06F21/81 , G06F1/14 , G06F1/28
CPC分类号： G06F21/81 , G01R31/31719 , G06F1/14 , G06F1/28
摘要： A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.
摘要翻译：提供了一种在检测到异常状况时限制对集成电路（IC）的访问的方法和装置。以低功耗提供异常电压检测，异常温度检测和异常时钟检测中的至少一种。可以检测异常低和异常高的参数值（例如异常低或高电压，温度或时钟频率）。异常时钟检测还可以检测停止的时钟信号，包括以低逻辑电平或高逻辑电平停止的时钟信号。此外，异常时钟检测可以检测时钟信号的异常占空比。采样的带隙基准可用于提供精确的电压和电流参考，同时消耗最小的功率。当检测到异常参数值时，可以提供一个或多个篡改指示以启动篡改对策，例如限制对IC的访问。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式