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1. 发明申请

US20160181380A1 Semiconductor Device Metal-Insulator-Semiconductor Contacts with Interface Layers and Methods for Forming the Same 审中-公开
标题翻译：半导体器件金属绝缘体 - 具有界面层的半导体触点及其形成方法
公开(公告)号：US20160181380A1
公开(公告)日：2016-06-23
申请号：US14576597
申请日：2014-12-19
申请人： Intermolecular Inc. , Global Foundries, Inc.
发明人： Amol Joshi , Sean Barstow , Paul Besser , Ashish Bodke , Guillaume Bouche , Nobumichi Fuchigami , Zhendong Hong , Shaoming Koh , Albert Sanghyup Lee , Salil Mujumdar , Abhijit Pethe , Mark Victor Raymond
IPC分类号： H01L29/417 , H01L21/285 , H01L29/66 , H01L21/02 , H01L29/45 , H01L29/78
CPC分类号： H01L21/28568 , H01L21/02186 , H01L21/02362 , H01L21/28512 , H01L21/76831 , H01L21/76843 , H01L29/47 , H01L29/66643 , H01L29/78 , H01L29/7839
摘要： Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. A source region and a drain region are formed on the semiconductor substrate. A gate electrode is formed between the source region and the drain region. A contact is formed above at least one of the source region and the drain region. The contact includes an insulating layer formed above the semiconductor substrate, an interface layer formed above the insulating layer, and a metallic layer formed above the interface layer. The interface layer is operable as a barrier between a material of the insulating layer and a material of the metallic layer, reduces the electrical resistance between the material of the insulating layer and the material of the metallic layer, or a combination thereof.
摘要翻译：本文提供的实施例描述了用于形成半导体器件的系统和方法。提供半导体衬底。源极区和漏极区形成在半导体衬底上。在源极区域和漏极区域之间形成栅电极。在源极区域和漏极区域中的至少一个上方形成接触。触点包括形成在半导体衬底之上的绝缘层，形成在绝缘层之上的界面层以及形成在界面层之上的金属层。界面层可用作绝缘层的材料和金属层的材料之间的屏障，减小了绝缘层的材料与金属层的材料之间的电阻或其组合。

2. 发明授权

US09196475B2 Methods for fabricating integrated circuits including fluorine incorporation 有权
标题翻译：包括氟掺入的集成电路的制造方法
公开(公告)号：US09196475B2
公开(公告)日：2015-11-24
申请号：US14253906
申请日：2014-04-16
申请人： GLOBALFOUNDRIES, Inc. , Intermolecular, Inc.
发明人： Bongki Lee , Paul Besser , Kevin Kashefi , Olov Karlsson , Ashish Bodke , Ratsamee Limdulpaiboon , Divya Pisharoty , Nobi Fuchigami
IPC分类号： H01L23/48 , H01L21/02 , H01L21/28 , H01L29/51
CPC分类号： H01L21/02181 , H01L21/02164 , H01L21/02321 , H01L21/0234 , H01L21/02362 , H01L21/28176 , H01L21/28185 , H01L21/28202 , H01L21/3105 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.
摘要翻译：提供了用于制造集成电路的集成电路和方法。在一个示例中，制造集成电路的方法包括在FET区域中形成电介质氧化物材料的中间层并覆盖在半导体衬底上。沉积在中间层上方的高K电介质层。氟被并入到中间层和/或高K电介质层中。

3. 发明申请

US20170104031A1 Selector Elements 审中-公开
公开(公告)号：US20170104031A1
公开(公告)日：2017-04-13
申请号：US15287091
申请日：2016-10-06
申请人： Intermolecular, Inc.
发明人： Mark Clark , Prashant Phatak , Charlene Chen , Ashish Bodke , Salil Mujumdar , Federico Nardi , Satbir Kahlon , Sergey V. Barabash , Feihu Wang
IPC分类号： H01L27/24 , G11C11/16 , G11C13/00 , H01L45/00 , H01L27/22
CPC分类号： G11C11/1659 , G11C13/003 , G11C2213/53 , G11C2213/72 , G11C2213/76 , H01L27/224 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/143 , H01L45/144
摘要： Provided are selector elements with active components comprising insulating matrices and mobile ions disposed within these insulating matrices. Also provided are methods of operating such selector elements. The insulating matrices and mobile ions may be formed from different combinations of materials. For example, the insulating matrix may comprise amorphous silicon or silicon oxide, while mobile ions may be silver ions. In another example, the active component comprises copper and germanium, selenium, or tellerium, e.g., Se61Cu39, Se67Cu33, or Se56Cu44. The active component may be a multilayered structure with a variable composition throughout the structure. For example, the concentration of mobile ions may be higher in a center of the structure, away from the electrode interfaces. In some embodiments, outer layers may be formed from Ge33Se24Cu47, while the middle layer may be formed from Ge47Se29Cu24.

4. 发明申请

US20150091105A1 CONTINUOUS TUNING OF ERBIUM SILICIDE METAL GATE EFFECTIVE WORK FUNCTION VIA A PVD NANOLAMINATE APPROACH FOR MOSFET APPLICATIONS 有权
标题翻译：通过用于MOSFET应用的PVD纳米铝酸盐方法，连续调节硅酸铝金属栅极有效的工作功能
公开(公告)号：US20150091105A1
公开(公告)日：2015-04-02
申请号：US14090822
申请日：2013-11-26
申请人： Intermolecular Inc.
发明人： Zhendong Hong , Ashish Bodke , Olov Karlsson
IPC分类号： H01L29/49 , H01L29/66 , H01L29/78 , H01L21/28
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66795 , H01L29/78 , H01L29/7833
摘要： Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nano-laminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack.
摘要翻译：矽硅化物层可用于CMOS晶体管，其中铒硅化物层的功函数可调谐用于PMOS和NMOS器件。可以使用纳米层压溅射方法，其中交替沉积硅和铒层以确定特定栅极堆叠的最佳层性质，组成分布和铒与硅比。

5. 发明授权

US08945414B1 Oxide removal by remote plasma treatment with fluorine and oxygen radicals 有权
标题翻译：用氟和氧自由基通过远程等离子体处理除去氧化物
公开(公告)号：US08945414B1
公开(公告)日：2015-02-03
申请号：US14079442
申请日：2013-11-13
申请人： Intermolecular Inc.
发明人： Jingang Su , Ashish Bodke , Abhijit Pethe , J Watanabe
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00 , H01L21/3065 , H01L21/02
CPC分类号： H01L21/31116 , H01J37/32357 , H01J2237/334 , H01L21/02046 , H01L22/12 , H01L22/26
摘要： Oxides (e.g., native or thermal silicon oxide) are etched from underlying silicon with a mixture of fluorine and oxygen radicals generated by a remote plasma. The oxygen radicals rapidly oxidize any uncovered bare silicon areas, preventing the pitting that can result from fluorine etching bare silicon more rapidly than it etches the surrounding oxide. A very thin (few Å), highly uniform passivation layer remaining on the silicon after the process may be left in place or removed. An oxygen-impermeable layer may be formed in-situ immediately afterward to prevent further oxidation. A pre-treatment with oxygen radicals alone fills pores and gaps in the oxide before etching begins.
摘要翻译：通过由远程等离子体产生的氟和氧自由基的混合物从下面的硅蚀刻氧化物（例如天然或热氧化硅）。氧自由基快速氧化任何未覆盖的裸硅区域，防止氟蚀刻裸硅的点蚀比其蚀刻周围氧化物更快。在该过程之后残留在硅上的非常薄（几埃）的高度均匀的钝化层可能留在原位或去除。可以立即就地形成不透氧层，以防止进一步的氧化。单独的氧自由基的预处理在蚀刻开始之前填充氧化物中的孔隙和间隙。

6. 发明授权

US09455393B1 Low temperature deposition of low loss dielectric layers in superconducting circuits 有权
标题翻译：超导电路中低损耗介电层的低温沉积
公开(公告)号：US09455393B1
公开(公告)日：2016-09-27
申请号：US14981163
申请日：2015-12-28
申请人： Intermolecular, Inc.
发明人： Ashish Bodke , Frank Greer , Mark Clark
IPC分类号： H01L29/06 , H01L29/08 , H01L39/24 , H01L39/02
CPC分类号： H01L39/2493 , H01L27/18
摘要： Provided are superconducting circuits and method of forming thereof. A superconducting circuit may include a low loss dielectric (LLD) layer formed from one or both of polycrystalline silicon or polycrystalline germanium. The LLD layer may be formed at a low temperature (e.g., less than about 525° C.) using chemical vapor deposition (CVD). Addition of germanium may help to lower the deposition temperature and improve crystallinity of the resulting layer. The LLD layer is formed without adding silicides at the interface of the LLD layer and metal electrode. In some embodiments, an initial layer (e.g., a seed layer or a protective layer) may be formed on a metal electrode prior to forming the LLD layer. For example, the initial layer may include one of zinc sulfide, polycrystalline germanium, or polycrystalline silicon. The initial layer may be deposited at a low pressure (e.g., less than 10 Torr) to ensure higher levels of crystallinity.
摘要翻译：提供超导电路及其形成方法。超导电路可以包括由多晶硅或多晶锗中的一个或两者形成的低损耗电介质（LLD）层。可以使用化学气相沉积（CVD）在低温（例如，小于约525℃）下形成LLD层。添加锗可能有助于降低沉积温度并改善所得层的结晶度。在LLD层和金属电极的界面处不添加硅化物形成LLD层。在一些实施例中，可以在形成LLD层之前在金属电极上形成初始层（例如种子层或保护层）。例如，初始层可以包括硫化锌，多晶锗或多晶硅中的一种。初始层可以以低压（例如，小于10托）沉积以确保更高水平的结晶度。

7. 发明申请

US20140363942A1 Method for forming a low resistivity tungsten silicide layer for metal gate stack applications 审中-公开
标题翻译：用于形成用于金属栅极堆叠应用的低电阻率硅化钨层的方法
公开(公告)号：US20140363942A1
公开(公告)日：2014-12-11
申请号：US13915324
申请日：2013-06-11
申请人： Intermolecular Inc.
发明人： Zhendong Hong , Ashish Bodke , Susie Tzeng
IPC分类号： H01L21/28 , H01L29/66
CPC分类号： H01L21/28097 , H01L21/324 , H01L29/4975 , H01L29/66795 , H01L29/785
摘要： Tungsten silicide layers can be used in CMOS transistors in which the work function of the tungsten silicide layers can be tuned for use in PMOS and NMOS devices. A co-sputtering approach can be used in which silicon and tungsten are deposited on a high dielectric constant gate dielectric layer. The tungsten silicide layer can be annealed at or above a critical temperature to optimize the resistivity of the tungsten silicide layer. In some embodiments, the concentration of as-deposited tungsten silicide can be between 50 at % silicon to 80 at % silicon. The critical temperatures can be lower at higher silicon concentration, such as 700 C. at 63 at % silicon to 600 C. at 74 at % silicon.
摘要翻译：硅化钨层可用于CMOS晶体管，其中硅化钨层的功函数可调谐用于PMOS和NMOS器件。可以使用共溅射方法，其中硅和钨沉积在高介电常数栅极电介质层上。硅化钨层可以在临界温度以上或高于临界温度退火，以优化硅化钨层的电阻率。在一些实施例中，沉积的硅化钨的浓度可以在50at％的硅与80at％的硅之间。较高的硅浓度，例如700℃，63at％硅至600℃，74at％的硅，临界温度可以较低。

8. 发明申请

US20140262749A1 Methods of Plasma Surface Treatment in a PVD Chamber 审中-公开
标题翻译： PVD室中等离子体表面处理方法
公开(公告)号：US20140262749A1
公开(公告)日：2014-09-18
申请号：US13804265
申请日：2013-03-14
申请人： Intermolecular, Inc.
发明人： Ashish Bodke , Olov Karlsson , Kevin Kashefi , Chi-I Lang , Dipankar Pramanik , Hong Sheng Yang , Xuena Zhang
IPC分类号： C23C14/35
CPC分类号： B01J19/0046 , B01J2219/0043 , B01J2219/00443 , B01J2219/00527 , B01J2219/00635 , B01J2219/0075 , B01J2219/00756 , C23C14/042 , C23C14/345
摘要： Combinatorial processing of a substrate comprising site-isolated sputter deposition and site-isolated plasma processing can be performed in a same process chamber. The process chamber, configured to perform sputter deposition and plasma processing, comprises a grounded shield having at least an aperture disposed above the substrate to form a small, dark space gap to reduce or eliminate any plasma formation within the gap. The plasma processing may include plasma etching or plasma surface treatment.
摘要翻译：包含现场分离的溅射沉积和位置分离等离子体处理的基板的组合处理可以在相同的处理室中进行。被配置为执行溅射沉积和等离子体处理的处理室包括接地屏蔽，其具有设置在衬底上方的至少一个孔，以形成小的，较暗的空间间隙，以减少或消除间隙内的任何等离子体形成。等离子体处理可以包括等离子体蚀刻或等离子体表面处理。

9. 发明申请

US20170062522A1 Combining Materials in Different Components of Selector Elements of Integrated Circuits 审中-公开
标题翻译：将材料组合在集成电路选择元件的不同组件中
公开(公告)号：US20170062522A1
公开(公告)日：2017-03-02
申请号：US15235992
申请日：2016-08-12
申请人： Intermolecular, Inc.
发明人： Salil Mujumdar , Abhijit Pethe , Ashish Bodke , Kevin Kashefi
IPC分类号： H01L27/24 , G11C13/00 , H01L45/00
CPC分类号： H01L27/24 , G11C11/1659 , G11C13/003 , G11C2213/15 , G11C2213/52 , G11C2213/72 , H01L27/2409 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/145 , H01L45/148
摘要： Provided are selector elements having snapback characteristics and non-volatile memory cells comprising such selector elements. To achieve its snapback characteristic, a selector element may include a dielectric layer comprising an alloy of two or more materials. In the same or other embodiments, the selector element may include a doped electrode, such carbon electrodes doped with silicon, germanium, and/or selenium. Concentrations of different materials forming an alloy may vary throughout the thickness of the dielectric layer. For example, the concentration of the first one alloy material may be higher in the center of the dielectric layer than near the interfaces of the dielectric layer with the electrodes. Some examples of this alloy material include germanium, indium, and aluminum. Examples of other materials in the same alloy include silicon, gallium, arsenic, and antimony. In some embodiments, the alloy is formed by three or more elements, such as indium gallium arsenic.
摘要翻译：提供具有快速恢复特性的选择器元件和包括这种选择器元件的非易失性存储单元。为了实现其回跳特性，选择器元件可以包括包含两种或更多种材料的合金的电介质层。在相同或其它实施例中，选择器元件可以包括掺杂电极，掺杂有硅，锗和/或硒的碳电极。形成合金的不同材料的浓度可以在电介质层的整个厚度上变化。例如，第一种合金材料的浓度在电介质层的中心处可以比在具有电极的介电层的界面附近更高。该合金材料的一些实例包括锗，铟和铝。相同合金中的其它材料的实例包括硅，镓，砷和锑。在一些实施例中，合金由三种或更多种元素形成，例如铟镓砷。

10. 发明申请

US20160149129A1 Using Metal Silicides as Electrodes for MSM Stack in Selector for Non-Volatile Memory Application 审中-公开
标题翻译：使用金属硅化物作为选择器中MSM堆叠的电极用于非易失性存储器应用
公开(公告)号：US20160149129A1
公开(公告)日：2016-05-26
申请号：US14553632
申请日：2014-11-25
申请人： Intermolecular, Inc.
发明人： Ashish Bodke , Mark Clark , Kevin Kashefi , Prashant B. Phatak , Dipankar Pramanik
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , H01L27/2409 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253
摘要： Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The metal layer of the selector element can include conductive materials such as metal silicides, and metal silicon nitrides. Conductive materials of the MSM may include tantalum silicide, tantalum silicon nitride, titanium silicide, titanium silicon nitride, or combinations thereof.
摘要翻译：公开了适用于非易失性存储器件应用的选择元件。选择器元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及在较高电压下更高的漏电流，以最大限度地减少器件切换期间的电压降。选择器元件可以基于多层膜堆叠（例如金属 - 半导体 - 金属（MSM）堆叠）。选择元件的金属层可以包括诸如金属硅化物的导电材料和金属硅氮化物。 MSM的导电材料可以包括硅化钽，氮化钽，硅化钛，氮化钛或其组合。

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