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1. 发明授权

US07024498B2 Apparatus for receiving data packet eliminating the need of a temporary memory and memory controller and method thereof 有权
标题翻译：用于接收数据分组而不需要临时存储器和存储器控制器的装置及其方法
公开(公告)号：US07024498B2
公开(公告)日：2006-04-04
申请号：US10460919
申请日：2003-06-13
申请人： Jae Sung Lee , Young Woo Kim , Sung Nam Kim , Sang Man Moh , Yong Youn Kim , Myung Joon Kim , Kee Wook Rim
发明人： Jae Sung Lee , Young Woo Kim , Sung Nam Kim , Sang Man Moh , Yong Youn Kim , Myung Joon Kim , Kee Wook Rim
IPC分类号： G06F3/00
CPC分类号： H04L1/0061 , H04L1/0045 , H04L49/90 , H04L49/9063
摘要： A device for effectively and economically receiving a packet by eliminating temporary memory and a memory controller. The apparatus includes an inspection logic circuit for inspecting data units as soon as they arrive in order to find an error included in the packet and generating control signals according to a result of inspecting a data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units have arrived; and FIFO memories for receiving the data unit, storing the data unit in a corresponding one of FIFO memories and either deleting or completing storing data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the device by eliminating a temporary memory and a memory controller for the temporary memory and can also reduce processing time.
摘要翻译：一种用于通过消除临时存储器和存储器控制器来有效且经济地接收分组的装置。该装置包括检查逻辑电路，用于在数据单元到达时检查数据单元，以便找到分组中包含的错误，并根据检查数据单元的结果产生控制信号; 多路复用器，用于在数据单元到达之后接收数据单元并分发所接收的数据单元; 和FIFO存储器，用于接收数据单元，将数据单元存储在相应的一个FIFO存储器中，并根据来自检查逻辑电路的控制信号删除或完成存储数据单元。本发明可以通过消除用于临时存储器的临时存储器和存储器控制器来降低设备的制造成本，并且还可以减少处理时间。

2. 发明授权

US06853588B2 First-in first-out memory circuit and method for executing same 有权
标题翻译：先进先出的存储电路及其执行方法
公开(公告)号：US06853588B2
公开(公告)日：2005-02-08
申请号：US10631763
申请日：2003-08-01
申请人： Youngwoo Kim , Jae Sung Lee , Kyoung Park , Sang Man Moh , Yong Youn Kim , Myung-Joon Kim , Kee-Wook Rim
发明人： Youngwoo Kim , Jae Sung Lee , Kyoung Park , Sang Man Moh , Yong Youn Kim , Myung-Joon Kim , Kee-Wook Rim
IPC分类号： G11C7/00 , G11C8/04 , G11C16/04
CPC分类号： G11C8/04
摘要： In a first-in first-out memory circuit using a standard cell library memory, a memory block includes N number of memories (N>1). A read pointer designates read addresses of the N number of memories. A write pointer designates write addresses of the N number of memories. A memory controller selects one from the N number of memories based on the read/write addresses, generates n number of read/write clock signals by demultiplying a clock signal by n (n=N, n>1) and sends the n number of read/write clock signals having a 1/n cycle difference to the N number of memories thereby inputting/outputting data.
摘要翻译：在使用标准单元库存储器的先进先出存储器电路中，存储块包括N个存储器（N> 1）。读指针指定N个存储器的读地址。写指针指定N个存储器的写地址。存储器控制器基于读/写地址从N个存储器中选择一个，通过将时钟信号递减n（n = N，n> 1）来生成n个读/写时钟信号，并发送n个对N个存储器具有1 / n个周期差的读/写时钟信号，从而输入/输出数据。

3. 发明授权

US06711643B2 Method and apparatus for interrupt redirection for arm processors 有权
标题翻译：用于臂处理器的中断重定向的方法和装置
公开(公告)号：US06711643B2
公开(公告)日：2004-03-23
申请号：US10028702
申请日：2001-12-28
申请人： Kyoung Park , Sang Man Moh , Yong Youn Kim
发明人： Kyoung Park , Sang Man Moh , Yong Youn Kim
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： Disclosed herein is an interrupt redirection apparatus and method for inter-processor communication. The apparatus includes a plurality of ARM processors, a vectored interrupt controller, an interrupt command register, an interrupt data register for designating the contents of each interrupt, an interrupt signal generation unit, and a bus interface unit used for providing read and write accesses of both the interrupt command register and the interrupt data register. The vectored interrupt controller for receiving interrupts generated by hardware for performing a specific function under the control of each ARM processor and interrupts generated by peripheral hardware, and transferring each interrupt as each interrupt request signal to an ARM processor designated as a master processor. The interrupt command register designates targets and kinds of each interrupt to perform a function for receiving an interrupt redirection command and activating an interrupt request signal. The interrupt signal generation unit reads the contents and activates an interrupt request signal.
摘要翻译：这里公开了一种用于处理器间通信的中断重定向装置和方法。该装置包括多个ARM处理器，向量中断控制器，中断命令寄存器，用于指定每个中断内容的中断数据寄存器，中断信号生成单元和总线接口单元，用于提供读取和写入访问中断命令寄存器和中断数据寄存器。矢量中断控制器，用于接收由硬件产生的中断，用于在每个ARM处理器的控制下执行特定功能并由外围硬件产生中断，并将每个中断请求信号作为每个中断请求信号传送到指定为主处理器的ARM处理器。中断命令寄存器指定每个中断的目标和种类，以执行接收中断重定向命令和激活中断请求信号的功能。中断信号生成单元读取内容并激活中断请求信号。

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