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1. 发明授权

US07024498B2 Apparatus for receiving data packet eliminating the need of a temporary memory and memory controller and method thereof 有权
标题翻译：用于接收数据分组而不需要临时存储器和存储器控制器的装置及其方法
公开(公告)号：US07024498B2
公开(公告)日：2006-04-04
申请号：US10460919
申请日：2003-06-13
申请人： Jae Sung Lee , Young Woo Kim , Sung Nam Kim , Sang Man Moh , Yong Youn Kim , Myung Joon Kim , Kee Wook Rim
发明人： Jae Sung Lee , Young Woo Kim , Sung Nam Kim , Sang Man Moh , Yong Youn Kim , Myung Joon Kim , Kee Wook Rim
IPC分类号： G06F3/00
CPC分类号： H04L1/0061 , H04L1/0045 , H04L49/90 , H04L49/9063
摘要： A device for effectively and economically receiving a packet by eliminating temporary memory and a memory controller. The apparatus includes an inspection logic circuit for inspecting data units as soon as they arrive in order to find an error included in the packet and generating control signals according to a result of inspecting a data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units have arrived; and FIFO memories for receiving the data unit, storing the data unit in a corresponding one of FIFO memories and either deleting or completing storing data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the device by eliminating a temporary memory and a memory controller for the temporary memory and can also reduce processing time.
摘要翻译：一种用于通过消除临时存储器和存储器控制器来有效且经济地接收分组的装置。该装置包括检查逻辑电路，用于在数据单元到达时检查数据单元，以便找到分组中包含的错误，并根据检查数据单元的结果产生控制信号; 多路复用器，用于在数据单元到达之后接收数据单元并分发所接收的数据单元; 和FIFO存储器，用于接收数据单元，将数据单元存储在相应的一个FIFO存储器中，并根据来自检查逻辑电路的控制信号删除或完成存储数据单元。本发明可以通过消除用于临时存储器的临时存储器和存储器控制器来降低设备的制造成本，并且还可以减少处理时间。

2. 发明授权

US6023732A Message transfer apparatus for controlling a message send in a packet switched interconnection network 失效
标题翻译：用于控制在分组交换互连网络中发送的消息的消息传送装置
公开(公告)号：US6023732A
公开(公告)日：2000-02-08
申请号：US899957
申请日：1997-07-24
申请人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
发明人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
IPC分类号： H04L12/54 , H04L12/861 , H04L12/879 , H04L12/00 , G06F15/16
CPC分类号： H04L49/901 , H04L12/5693 , H04L49/90
摘要： The present invention relates to a message-passing computer system and a packet-switched interconnection network. The message transfer apparatus in a packet-switched interconnection network includes a message send controller controlling a send procedure in which messages requested by a processor are sent via an output port, and a timer enabled by an output signal of the message send controller and generating a timeout signal. A buffer unit is connected to the message send controller and is composed of a message buffer having four buffers and a data buffer. A local bus controller connects the message send controller and the buffer unit to the local bus and controls a transfer request and a transfer response to the local bus. An output port controller connected to both the message send controller and the buffer unit controls the output port which sends a packet to an interconnection network.
摘要翻译：本发明涉及消息传递计算机系统和分组交换互连网络。分组交换互连网络中的消息传送装置包括控制发送过程的消息发送控制器，其中经由输出端口发送由处理器请求的消息，以及由消息发送控制器的输出信号启用的定时器，超时信号缓冲单元连接到消息发送控制器，并由具有四个缓冲器和数据缓冲器的消息缓冲器组成。本地总线控制器将消息发送控制器和缓冲器单元连接到本地总线，并控制传输请求和对本地总线的传输响应。连接到消息发送控制器和缓冲器单元的输出端口控制器控制向互连网络发送分组的输出端口。

3. 发明授权

US5910178A Method for controlling a message send in a packet-switched interconnection network 失效
标题翻译：用于控制在分组交换互连网络中发送的消息的方法
公开(公告)号：US5910178A
公开(公告)日：1999-06-08
申请号：US899552
申请日：1997-07-24
申请人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
发明人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
IPC分类号： H04L12/54 , H04L12/861 , H04L12/879 , H04L12/00 , G06F15/16
CPC分类号： H04L49/901 , H04L12/5693 , H04L49/90
摘要： The present invention discloses a method for controlling a message send in a packet-switched interconnection network, which incorporates a message send controller supporting an efficient message send and a dedicated hardware capable of maximizing a message send rate, taking the structural characteristics of the message-passing parallel computer system method into maximum considerations, thereby minimizing software and hardware overhead in sending a message and being capable of selecting a message send method in accordance with the message characteristics.
摘要翻译：本发明公开了一种用于控制分组交换互联网络中的消息发送的方法，其包括支持有效消息发送的消息发送控制器和能够最大化消息发送速率的专用硬件，采用消息发送的结构特征，通过并行计算机系统方法进行最大限度的考虑，从而最小化发送消息时的软件和硬件开销，并根据消息特性选择消息发送方法。

4. 发明授权

US6061345A Crossbar routing switch for a hierarchical crossbar interconnection network 失效
标题翻译：交叉开关用于分层交叉网络互连网络
公开(公告)号：US6061345A
公开(公告)日：2000-05-09
申请号：US941130
申请日：1997-09-30
申请人： Jong Seok Hahn , Kyoung Park , Woo Jong Hahn , Kee Wook Rim
发明人： Jong Seok Hahn , Kyoung Park , Woo Jong Hahn , Kee Wook Rim
IPC分类号： G06F15/16 , H04L12/701 , H04L12/775 , H04L12/931 , H04L12/933 , H04L12/935 , H04L12/947 , H04L12/28 , H04L12/56 , H04Q19/00
CPC分类号： H04L49/1576 , H04L45/00 , H04L45/583 , H04L49/101 , H04L49/256 , H04L49/45 , H04L49/30
摘要： A routing switch for constructing an interconnection network of a parallel processing computer is disclosed. A purpose of the present invention is to provide a crossbar routing switch for a hierarchical interconnection network which has an expandability of a data length and an expandability of a hierarchical structure. The crossbar routing switch for a hierarchical interconnection network in accordance with the present invention comprises a predetermined number of input control units for controlling one input port to perform the manipulation of input data; a crossbar core unit for analyzing a data transmission request by the input control unit and outputting the corresponding data; and a predetermined number of output control unit for controlling one output port and receiving the output data from the crossbar core unit to output it to the output port. The present invention has advantages over the prior art that a data expandability can be provided by simply adding a routing switch without re-designing or re-manufacturing the routing switch several times, and that it can be suitably adapted to an interconnection network of a parallel processing system which requires a high expandability and high performance.
摘要翻译：公开了一种用于构建并行处理计算机的互连网络的路由交换机。本发明的目的是提供一种具有数据长度的可扩展性和分级结构的可扩展性的分级互连网络的交叉开关。根据本发明的用于分层互连网络的交叉开关路由开关包括用于控制一个输入端口以执行输入数据的操纵的预定数量的输入控制单元; 横杆核心单元，用于分析由输入控制单元进行的数据传输请求并输出相应的数据; 以及预定数量的输出控制单元，用于控制一个输出端口并接收来自交叉开关核心单元的输出数据以将其输出到输出端口。本发明具有优于现有技术的优点，通过简单地添加路由交换机而不需要重新设计或重新制造路由交换机多次即可提供数据扩展性，并且可以适当地适应于并行的互连网络处理系统需要高扩展性和高性能。

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