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1. 发明授权

US07024498B2 Apparatus for receiving data packet eliminating the need of a temporary memory and memory controller and method thereof 有权
标题翻译：用于接收数据分组而不需要临时存储器和存储器控制器的装置及其方法
公开(公告)号：US07024498B2
公开(公告)日：2006-04-04
申请号：US10460919
申请日：2003-06-13
申请人： Jae Sung Lee , Young Woo Kim , Sung Nam Kim , Sang Man Moh , Yong Youn Kim , Myung Joon Kim , Kee Wook Rim
发明人： Jae Sung Lee , Young Woo Kim , Sung Nam Kim , Sang Man Moh , Yong Youn Kim , Myung Joon Kim , Kee Wook Rim
IPC分类号： G06F3/00
CPC分类号： H04L1/0061 , H04L1/0045 , H04L49/90 , H04L49/9063
摘要： A device for effectively and economically receiving a packet by eliminating temporary memory and a memory controller. The apparatus includes an inspection logic circuit for inspecting data units as soon as they arrive in order to find an error included in the packet and generating control signals according to a result of inspecting a data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units have arrived; and FIFO memories for receiving the data unit, storing the data unit in a corresponding one of FIFO memories and either deleting or completing storing data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the device by eliminating a temporary memory and a memory controller for the temporary memory and can also reduce processing time.
摘要翻译：一种用于通过消除临时存储器和存储器控制器来有效且经济地接收分组的装置。该装置包括检查逻辑电路，用于在数据单元到达时检查数据单元，以便找到分组中包含的错误，并根据检查数据单元的结果产生控制信号; 多路复用器，用于在数据单元到达之后接收数据单元并分发所接收的数据单元; 和FIFO存储器，用于接收数据单元，将数据单元存储在相应的一个FIFO存储器中，并根据来自检查逻辑电路的控制信号删除或完成存储数据单元。本发明可以通过消除用于临时存储器的临时存储器和存储器控制器来降低设备的制造成本，并且还可以减少处理时间。

2. 发明授权

US06853588B2 First-in first-out memory circuit and method for executing same 有权
标题翻译：先进先出的存储电路及其执行方法
公开(公告)号：US06853588B2
公开(公告)日：2005-02-08
申请号：US10631763
申请日：2003-08-01
申请人： Youngwoo Kim , Jae Sung Lee , Kyoung Park , Sang Man Moh , Yong Youn Kim , Myung-Joon Kim , Kee-Wook Rim
发明人： Youngwoo Kim , Jae Sung Lee , Kyoung Park , Sang Man Moh , Yong Youn Kim , Myung-Joon Kim , Kee-Wook Rim
IPC分类号： G11C7/00 , G11C8/04 , G11C16/04
CPC分类号： G11C8/04
摘要： In a first-in first-out memory circuit using a standard cell library memory, a memory block includes N number of memories (N>1). A read pointer designates read addresses of the N number of memories. A write pointer designates write addresses of the N number of memories. A memory controller selects one from the N number of memories based on the read/write addresses, generates n number of read/write clock signals by demultiplying a clock signal by n (n=N, n>1) and sends the n number of read/write clock signals having a 1/n cycle difference to the N number of memories thereby inputting/outputting data.
摘要翻译：在使用标准单元库存储器的先进先出存储器电路中，存储块包括N个存储器（N> 1）。读指针指定N个存储器的读地址。写指针指定N个存储器的写地址。存储器控制器基于读/写地址从N个存储器中选择一个，通过将时钟信号递减n（n = N，n> 1）来生成n个读/写时钟信号，并发送n个对N个存储器具有1 / n个周期差的读/写时钟信号，从而输入/输出数据。

3. 发明授权

US06871237B2 System for controlling data transfer protocol with a host bus interface 有权
标题翻译：用于通过主机总线接口控制数据传输协议的系统
公开(公告)号：US06871237B2
公开(公告)日：2005-03-22
申请号：US10418127
申请日：2003-04-18
申请人： Jong Seok Han , Yong Seok Choi , Sang Man Moh , Myung-Joon Kim , Kee-Wook Rim
发明人： Jong Seok Han , Yong Seok Choi , Sang Man Moh , Myung-Joon Kim , Kee-Wook Rim
IPC分类号： G06F13/00 , G06F13/14 , G06F13/28
CPC分类号： G06F13/28
摘要： The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance. The data transfer protocol control system with a host bus interface includes a transmitting/receiving command DMA for instructing the command DMA request buffer to read and write command message data, a transmitting data DMA for instructing the transmitting data DMA request buffer to read the command message data, a receiving data DMA for instructing the receiving data DMA request buffer to write the command message data and a data transfer protocol control device for putting read information, write information and message data on a host bus, receiving message data and a transfer response signal and delivering the message data through the response buffer of the corresponding DMA.
摘要翻译：本发明是一种具有主机总线接口的数据传输协议控制系统，其包括发送/接收命令DMA，发送数据DMA和用于通过主机总线接口控制数据传输协议的接收数据DMA，考虑特性，使用频率，同时命令DMA和数据DMA的处理功能。主机接口总线被有效地使用，总线使用率正确分配，以适当地支持传输流程，并提高整个系统性能。具有主机总线接口的数据传输协议控制系统包括用于指令DMA请求缓冲器读取和写入命令消息数据的发送/接收命令DMA，用于指示发送数据DMA请求缓冲器读取命令消息的发送数据DMA 数据，用于指示接收数据DMA请求缓冲器写入命令消息数据的接收数据DMA和用于将读信息，写信息和消息数据放在主机总线上的数据传输协议控制装置，接收消息数据和传送响应信号并通过相应DMA的响应缓冲区传送消息数据。

4. 发明授权

US5910178A Method for controlling a message send in a packet-switched interconnection network 失效
标题翻译：用于控制在分组交换互连网络中发送的消息的方法
公开(公告)号：US5910178A
公开(公告)日：1999-06-08
申请号：US899552
申请日：1997-07-24
申请人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
发明人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
IPC分类号： H04L12/54 , H04L12/861 , H04L12/879 , H04L12/00 , G06F15/16
CPC分类号： H04L49/901 , H04L12/5693 , H04L49/90
摘要： The present invention discloses a method for controlling a message send in a packet-switched interconnection network, which incorporates a message send controller supporting an efficient message send and a dedicated hardware capable of maximizing a message send rate, taking the structural characteristics of the message-passing parallel computer system method into maximum considerations, thereby minimizing software and hardware overhead in sending a message and being capable of selecting a message send method in accordance with the message characteristics.
摘要翻译：本发明公开了一种用于控制分组交换互联网络中的消息发送的方法，其包括支持有效消息发送的消息发送控制器和能够最大化消息发送速率的专用硬件，采用消息发送的结构特征，通过并行计算机系统方法进行最大限度的考虑，从而最小化发送消息时的软件和硬件开销，并根据消息特性选择消息发送方法。

5. 发明授权

US6023732A Message transfer apparatus for controlling a message send in a packet switched interconnection network 失效
标题翻译：用于控制在分组交换互连网络中发送的消息的消息传送装置
公开(公告)号：US6023732A
公开(公告)日：2000-02-08
申请号：US899957
申请日：1997-07-24
申请人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
发明人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
IPC分类号： H04L12/54 , H04L12/861 , H04L12/879 , H04L12/00 , G06F15/16
CPC分类号： H04L49/901 , H04L12/5693 , H04L49/90
摘要： The present invention relates to a message-passing computer system and a packet-switched interconnection network. The message transfer apparatus in a packet-switched interconnection network includes a message send controller controlling a send procedure in which messages requested by a processor are sent via an output port, and a timer enabled by an output signal of the message send controller and generating a timeout signal. A buffer unit is connected to the message send controller and is composed of a message buffer having four buffers and a data buffer. A local bus controller connects the message send controller and the buffer unit to the local bus and controls a transfer request and a transfer response to the local bus. An output port controller connected to both the message send controller and the buffer unit controls the output port which sends a packet to an interconnection network.
摘要翻译：本发明涉及消息传递计算机系统和分组交换互连网络。分组交换互连网络中的消息传送装置包括控制发送过程的消息发送控制器，其中经由输出端口发送由处理器请求的消息，以及由消息发送控制器的输出信号启用的定时器，超时信号缓冲单元连接到消息发送控制器，并由具有四个缓冲器和数据缓冲器的消息缓冲器组成。本地总线控制器将消息发送控制器和缓冲器单元连接到本地总线，并控制传输请求和对本地总线的传输响应。连接到消息发送控制器和缓冲器单元的输出端口控制器控制向互连网络发送分组的输出端口。

6. 发明授权

US06711643B2 Method and apparatus for interrupt redirection for arm processors 有权
标题翻译：用于臂处理器的中断重定向的方法和装置
公开(公告)号：US06711643B2
公开(公告)日：2004-03-23
申请号：US10028702
申请日：2001-12-28
申请人： Kyoung Park , Sang Man Moh , Yong Youn Kim
发明人： Kyoung Park , Sang Man Moh , Yong Youn Kim
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： Disclosed herein is an interrupt redirection apparatus and method for inter-processor communication. The apparatus includes a plurality of ARM processors, a vectored interrupt controller, an interrupt command register, an interrupt data register for designating the contents of each interrupt, an interrupt signal generation unit, and a bus interface unit used for providing read and write accesses of both the interrupt command register and the interrupt data register. The vectored interrupt controller for receiving interrupts generated by hardware for performing a specific function under the control of each ARM processor and interrupts generated by peripheral hardware, and transferring each interrupt as each interrupt request signal to an ARM processor designated as a master processor. The interrupt command register designates targets and kinds of each interrupt to perform a function for receiving an interrupt redirection command and activating an interrupt request signal. The interrupt signal generation unit reads the contents and activates an interrupt request signal.
摘要翻译：这里公开了一种用于处理器间通信的中断重定向装置和方法。该装置包括多个ARM处理器，向量中断控制器，中断命令寄存器，用于指定每个中断内容的中断数据寄存器，中断信号生成单元和总线接口单元，用于提供读取和写入访问中断命令寄存器和中断数据寄存器。矢量中断控制器，用于接收由硬件产生的中断，用于在每个ARM处理器的控制下执行特定功能并由外围硬件产生中断，并将每个中断请求信号作为每个中断请求信号传送到指定为主处理器的ARM处理器。中断命令寄存器指定每个中断的目标和种类，以执行接收中断重定向命令和激活中断请求信号的功能。中断信号生成单元读取内容并激活中断请求信号。

7. 发明授权

US06415361B1 Apparatus for controlling cache by using dual-port transaction buffers 有权
标题翻译：用于通过使用双端口事务缓冲器来控制高速缓存的装置
公开(公告)号：US06415361B1
公开(公告)日：2002-07-02
申请号：US09487348
申请日：2000-01-19
申请人： Sang Man Moh , Jong Seok Han , An Do Ki , Woo Jong Hahn , Suk Han Yoon , Gil Rok Oh
发明人： Sang Man Moh , Jong Seok Han , An Do Ki , Woo Jong Hahn , Suk Han Yoon , Gil Rok Oh
IPC分类号： G06F1200
CPC分类号： G06F12/0828 , G06F2212/2542
摘要： An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.
摘要翻译：一种用于控制位于节点总线和互连网络之间以执行高速缓存一致性协议的计算节点中的高速缓存的装置包括：用于与节点总线接口的节点总线接口; 用于与互连网络对接的互连网络接口; 用于控制高速缓存以执行高速缓存一致性协议的高速缓存控制逻辑装置; 耦合在所述节点总线接口和所述高速缓存控制逻辑装置之间的总线端双端口事务缓冲器，用于缓冲从计算节点中包含的本地处理器请求和应答的事务; 以及耦合在所述互连网络接口和所述高速缓存控制逻辑之间的网络侧双端口事务缓冲器，用于缓存从耦合到互连网络的另一个计算节点中包含的远程处理器请求和回复的事务。

8. 发明授权

US06505289B1 Apparatus and method for interconnecting 3-link nodes and parallel processing apparatus using the same 有权
标题翻译：用于互连3链路节点的装置和方法以及使用其的并行处理装置
公开(公告)号：US06505289B1
公开(公告)日：2003-01-07
申请号：US09475049
申请日：1999-12-30
申请人： Jong Seok Han , Sang Man Moh , Woo Jong Hahn , Suk Han Yoon
发明人： Jong Seok Han , Sang Man Moh , Woo Jong Hahn , Suk Han Yoon
IPC分类号： G06F1300
CPC分类号： G06F15/17337
摘要： The present invention relates to a node connection apparatus. The 3-link node interconnection apparatus and parallel processing apparatus using the same confirm expanding nodes freely, only using fixed three connecting links, and are suitable to normal packaging method because of easy dividing into 2n (n>1) nodes. The apparatuses comprise the following nodes. The first node has three links connected to other nodes respectively. The second node has three links, one links of them is connected to the first node, and the other two links are in charge of connection of X+ direction, X− direction. The third node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Y+ direction, Y− direction. The fourth node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Z+ direction, Z− direction.
摘要翻译：节点连接装置技术领域本发明涉及节点连接装置。 3链节点互连设备和使用该链路节点的并行处理设备可以自由地确定扩展节点，只使用固定的三个连接链路，由于容易划分成2n（n> 1）个节点，因此适合正常的封装方法。这些装置包括以下节点。第一个节点分别连接到其他节点的三个链路。第二节点有三个链路，一个链路连接到第一个节点，另外两个链路负责连接X +方向，X方向。第三节点有三个链路，一个链路连接到第一个节点，另外两个链路负责Y +方向，Y方向的连接。第四个节点有三个链路，一个链路连接到第一个节点，另外两个链路负责Z +方向，Z方向的连接。

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