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1. 发明授权

US07024498B2 Apparatus for receiving data packet eliminating the need of a temporary memory and memory controller and method thereof 有权
标题翻译：用于接收数据分组而不需要临时存储器和存储器控制器的装置及其方法
公开(公告)号：US07024498B2
公开(公告)日：2006-04-04
申请号：US10460919
申请日：2003-06-13
申请人： Jae Sung Lee , Young Woo Kim , Sung Nam Kim , Sang Man Moh , Yong Youn Kim , Myung Joon Kim , Kee Wook Rim
发明人： Jae Sung Lee , Young Woo Kim , Sung Nam Kim , Sang Man Moh , Yong Youn Kim , Myung Joon Kim , Kee Wook Rim
IPC分类号： G06F3/00
CPC分类号： H04L1/0061 , H04L1/0045 , H04L49/90 , H04L49/9063
摘要： A device for effectively and economically receiving a packet by eliminating temporary memory and a memory controller. The apparatus includes an inspection logic circuit for inspecting data units as soon as they arrive in order to find an error included in the packet and generating control signals according to a result of inspecting a data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units have arrived; and FIFO memories for receiving the data unit, storing the data unit in a corresponding one of FIFO memories and either deleting or completing storing data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the device by eliminating a temporary memory and a memory controller for the temporary memory and can also reduce processing time.
摘要翻译：一种用于通过消除临时存储器和存储器控制器来有效且经济地接收分组的装置。该装置包括检查逻辑电路，用于在数据单元到达时检查数据单元，以便找到分组中包含的错误，并根据检查数据单元的结果产生控制信号; 多路复用器，用于在数据单元到达之后接收数据单元并分发所接收的数据单元; 和FIFO存储器，用于接收数据单元，将数据单元存储在相应的一个FIFO存储器中，并根据来自检查逻辑电路的控制信号删除或完成存储数据单元。本发明可以通过消除用于临时存储器的临时存储器和存储器控制器来降低设备的制造成本，并且还可以减少处理时间。

2. 发明授权

US6055599A Hierarchical crossbar interconnection network for a cluster-based parallel processing computer 失效
标题翻译：用于基于群集的并行处理计算机的分层交叉互连网络
公开(公告)号：US6055599A
公开(公告)日：2000-04-25
申请号：US143787
申请日：1998-08-31
申请人： Jong-Seok Han , Kyoung Park , Won-Sae Sim , Woo-Jong Hahn , Kee-Wook Rim
发明人： Jong-Seok Han , Kyoung Park , Won-Sae Sim , Woo-Jong Hahn , Kee-Wook Rim
IPC分类号： G06F15/173 , G06F13/00
CPC分类号： G06F15/17393
摘要： The present invention relates to a hierarchical crossbar inter-connection network for a cluster-based parallel processing computer. A crossbar network is composed of the "n" number of crossbar switches which is byte sliced, eight links for connecting eight nodes, and two links for connecting other clusters. In addition, one low-level cluster is formed by connecting a maximum of eight processing nodes between the two crossbar networks, and one high-level cluster is formed with a maximum of eight low-level clusters and the four crossbar networks. Moreover, one next high-level clusters formed with a maximum of eight high-level clusters and the eight crossbar networks for scalability.
摘要翻译：本发明涉及一种用于基于群集的并行处理计算机的层级交叉连接网络。交叉网络由“n”个字节切换的交叉开关组成，用于连接八个节点的八个链路和用于连接其他集群的两个链路组成。此外，通过在两个交叉网络之间连接最多八个处理节点来形成一个低级集群，并且一个高级集群形成有最多八个低级集群和四个交叉网络。此外，一个下一个高级别集群最多可组成八个高级集群，八个交叉网络可扩展。

3. 发明授权

US5964895A VRAM-based parity engine for use in disk array controller 失效
标题翻译：用于磁盘阵列控制器的基于VRAM的奇偶校验引擎
公开(公告)号：US5964895A
公开(公告)日：1999-10-12
申请号：US866801
申请日：1997-05-30
申请人： Jin-Pyo Kim , Joong-Bae Kim , Yong-Yun Kim , Kee-Wook Rim
发明人： Jin-Pyo Kim , Joong-Bae Kim , Yong-Yun Kim , Kee-Wook Rim
IPC分类号： G06F12/00 , G06F11/10 , G06F13/00
CPC分类号： G06F11/1076 , G06F2211/1009
摘要： A VRAM-based parity engine for use in a disk array controller is disclosed, in which the parity arithmetic operation is carried out in a fast and effective manner, thereby improving the performance of the RAID system. Particularly, the parity data arithmetic operation is not resorted to a processor, but to a VRAM, thereby realizing a high speed operation. In the disk array controller, a VRAM (video RAM) is used, in such a manner that the reading, updating and writing are made to be overlapped during the arithmetic operation, thereby promoting the speed of the arithmetic. Therefore, a relatively large capacity memory can be formed compared with the conventional SRAM, and therefore, a temporary buffer memory within the parity engine is used as a parity cache, thereby doubling the performance.
摘要翻译：公开了一种用于磁盘阵列控制器的基于VRAM的奇偶校验引擎，其中以快速有效的方式执行奇偶运算操作，从而提高RAID系统的性能。特别地，奇偶校验数据运算不是处理器，而是VRAM，从而实现高速操作。在磁盘阵列控制器中，使用VRAM（视频RAM），使得在算术运算期间读取，更新和写入被重叠，从而提高算术速度。因此，与常规SRAM相比，可以形成相对大的容量存储器，因此，奇偶校验引擎内的临时缓冲存储器被用作奇偶校验高速缓存，从而使性能增加一倍。

4. 发明授权

US5910178A Method for controlling a message send in a packet-switched interconnection network 失效
标题翻译：用于控制在分组交换互连网络中发送的消息的方法
公开(公告)号：US5910178A
公开(公告)日：1999-06-08
申请号：US899552
申请日：1997-07-24
申请人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
发明人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
IPC分类号： H04L12/54 , H04L12/861 , H04L12/879 , H04L12/00 , G06F15/16
CPC分类号： H04L49/901 , H04L12/5693 , H04L49/90
摘要： The present invention discloses a method for controlling a message send in a packet-switched interconnection network, which incorporates a message send controller supporting an efficient message send and a dedicated hardware capable of maximizing a message send rate, taking the structural characteristics of the message-passing parallel computer system method into maximum considerations, thereby minimizing software and hardware overhead in sending a message and being capable of selecting a message send method in accordance with the message characteristics.
摘要翻译：本发明公开了一种用于控制分组交换互联网络中的消息发送的方法，其包括支持有效消息发送的消息发送控制器和能够最大化消息发送速率的专用硬件，采用消息发送的结构特征，通过并行计算机系统方法进行最大限度的考虑，从而最小化发送消息时的软件和硬件开销，并根据消息特性选择消息发送方法。

5. 发明授权

US6023732A Message transfer apparatus for controlling a message send in a packet switched interconnection network 失效
标题翻译：用于控制在分组交换互连网络中发送的消息的消息传送装置
公开(公告)号：US6023732A
公开(公告)日：2000-02-08
申请号：US899957
申请日：1997-07-24
申请人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
发明人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
IPC分类号： H04L12/54 , H04L12/861 , H04L12/879 , H04L12/00 , G06F15/16
CPC分类号： H04L49/901 , H04L12/5693 , H04L49/90
摘要： The present invention relates to a message-passing computer system and a packet-switched interconnection network. The message transfer apparatus in a packet-switched interconnection network includes a message send controller controlling a send procedure in which messages requested by a processor are sent via an output port, and a timer enabled by an output signal of the message send controller and generating a timeout signal. A buffer unit is connected to the message send controller and is composed of a message buffer having four buffers and a data buffer. A local bus controller connects the message send controller and the buffer unit to the local bus and controls a transfer request and a transfer response to the local bus. An output port controller connected to both the message send controller and the buffer unit controls the output port which sends a packet to an interconnection network.
摘要翻译：本发明涉及消息传递计算机系统和分组交换互连网络。分组交换互连网络中的消息传送装置包括控制发送过程的消息发送控制器，其中经由输出端口发送由处理器请求的消息，以及由消息发送控制器的输出信号启用的定时器，超时信号缓冲单元连接到消息发送控制器，并由具有四个缓冲器和数据缓冲器的消息缓冲器组成。本地总线控制器将消息发送控制器和缓冲器单元连接到本地总线，并控制传输请求和对本地总线的传输响应。连接到消息发送控制器和缓冲器单元的输出端口控制器控制向互连网络发送分组的输出端口。

6. 发明授权

US06871237B2 System for controlling data transfer protocol with a host bus interface 有权
标题翻译：用于通过主机总线接口控制数据传输协议的系统
公开(公告)号：US06871237B2
公开(公告)日：2005-03-22
申请号：US10418127
申请日：2003-04-18
申请人： Jong Seok Han , Yong Seok Choi , Sang Man Moh , Myung-Joon Kim , Kee-Wook Rim
发明人： Jong Seok Han , Yong Seok Choi , Sang Man Moh , Myung-Joon Kim , Kee-Wook Rim
IPC分类号： G06F13/00 , G06F13/14 , G06F13/28
CPC分类号： G06F13/28
摘要： The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance. The data transfer protocol control system with a host bus interface includes a transmitting/receiving command DMA for instructing the command DMA request buffer to read and write command message data, a transmitting data DMA for instructing the transmitting data DMA request buffer to read the command message data, a receiving data DMA for instructing the receiving data DMA request buffer to write the command message data and a data transfer protocol control device for putting read information, write information and message data on a host bus, receiving message data and a transfer response signal and delivering the message data through the response buffer of the corresponding DMA.
摘要翻译：本发明是一种具有主机总线接口的数据传输协议控制系统，其包括发送/接收命令DMA，发送数据DMA和用于通过主机总线接口控制数据传输协议的接收数据DMA，考虑特性，使用频率，同时命令DMA和数据DMA的处理功能。主机接口总线被有效地使用，总线使用率正确分配，以适当地支持传输流程，并提高整个系统性能。具有主机总线接口的数据传输协议控制系统包括用于指令DMA请求缓冲器读取和写入命令消息数据的发送/接收命令DMA，用于指示发送数据DMA请求缓冲器读取命令消息的发送数据DMA 数据，用于指示接收数据DMA请求缓冲器写入命令消息数据的接收数据DMA和用于将读信息，写信息和消息数据放在主机总线上的数据传输协议控制装置，接收消息数据和传送响应信号并通过相应DMA的响应缓冲区传送消息数据。

7. 发明授权

US06853588B2 First-in first-out memory circuit and method for executing same 有权
标题翻译：先进先出的存储电路及其执行方法
公开(公告)号：US06853588B2
公开(公告)日：2005-02-08
申请号：US10631763
申请日：2003-08-01
申请人： Youngwoo Kim , Jae Sung Lee , Kyoung Park , Sang Man Moh , Yong Youn Kim , Myung-Joon Kim , Kee-Wook Rim
发明人： Youngwoo Kim , Jae Sung Lee , Kyoung Park , Sang Man Moh , Yong Youn Kim , Myung-Joon Kim , Kee-Wook Rim
IPC分类号： G11C7/00 , G11C8/04 , G11C16/04
CPC分类号： G11C8/04
摘要： In a first-in first-out memory circuit using a standard cell library memory, a memory block includes N number of memories (N>1). A read pointer designates read addresses of the N number of memories. A write pointer designates write addresses of the N number of memories. A memory controller selects one from the N number of memories based on the read/write addresses, generates n number of read/write clock signals by demultiplying a clock signal by n (n=N, n>1) and sends the n number of read/write clock signals having a 1/n cycle difference to the N number of memories thereby inputting/outputting data.
摘要翻译：在使用标准单元库存储器的先进先出存储器电路中，存储块包括N个存储器（N> 1）。读指针指定N个存储器的读地址。写指针指定N个存储器的写地址。存储器控制器基于读/写地址从N个存储器中选择一个，通过将时钟信号递减n（n = N，n> 1）来生成n个读/写时钟信号，并发送n个对N个存储器具有1 / n个周期差的读/写时钟信号，从而输入/输出数据。

8. 发明授权

US6061345A Crossbar routing switch for a hierarchical crossbar interconnection network 失效
标题翻译：交叉开关用于分层交叉网络互连网络
公开(公告)号：US6061345A
公开(公告)日：2000-05-09
申请号：US941130
申请日：1997-09-30
申请人： Jong Seok Hahn , Kyoung Park , Woo Jong Hahn , Kee Wook Rim
发明人： Jong Seok Hahn , Kyoung Park , Woo Jong Hahn , Kee Wook Rim
IPC分类号： G06F15/16 , H04L12/701 , H04L12/775 , H04L12/931 , H04L12/933 , H04L12/935 , H04L12/947 , H04L12/28 , H04L12/56 , H04Q19/00
CPC分类号： H04L49/1576 , H04L45/00 , H04L45/583 , H04L49/101 , H04L49/256 , H04L49/45 , H04L49/30
摘要： A routing switch for constructing an interconnection network of a parallel processing computer is disclosed. A purpose of the present invention is to provide a crossbar routing switch for a hierarchical interconnection network which has an expandability of a data length and an expandability of a hierarchical structure. The crossbar routing switch for a hierarchical interconnection network in accordance with the present invention comprises a predetermined number of input control units for controlling one input port to perform the manipulation of input data; a crossbar core unit for analyzing a data transmission request by the input control unit and outputting the corresponding data; and a predetermined number of output control unit for controlling one output port and receiving the output data from the crossbar core unit to output it to the output port. The present invention has advantages over the prior art that a data expandability can be provided by simply adding a routing switch without re-designing or re-manufacturing the routing switch several times, and that it can be suitably adapted to an interconnection network of a parallel processing system which requires a high expandability and high performance.
摘要翻译：公开了一种用于构建并行处理计算机的互连网络的路由交换机。本发明的目的是提供一种具有数据长度的可扩展性和分级结构的可扩展性的分级互连网络的交叉开关。根据本发明的用于分层互连网络的交叉开关路由开关包括用于控制一个输入端口以执行输入数据的操纵的预定数量的输入控制单元; 横杆核心单元，用于分析由输入控制单元进行的数据传输请求并输出相应的数据; 以及预定数量的输出控制单元，用于控制一个输出端口并接收来自交叉开关核心单元的输出数据以将其输出到输出端口。本发明具有优于现有技术的优点，通过简单地添加路由交换机而不需要重新设计或重新制造路由交换机多次即可提供数据扩展性，并且可以适当地适应于并行的互连网络处理系统需要高扩展性和高性能。

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