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1. 发明授权

US08405751B2 Image sensor pixel structure employing a shared floating diffusion 有权
标题翻译：采用共享浮动扩散的图像传感器像素结构
公开(公告)号：US08405751B2
公开(公告)日：2013-03-26
申请号：US12534427
申请日：2009-08-03
申请人： Jason D. Hibbeler , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel
发明人： Jason D. Hibbeler , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel
IPC分类号： H04N5/335
CPC分类号： H01L27/14609 , H01L27/14641 , H01L27/14643 , H04N5/37457
摘要： A pixel structure for an image sensor includes a semiconductor material portion having a coplanar and contiguous semiconductor surface and including four photodiodes, four channel regions, and a common floating diffusion region. Each of the four channel regions is directly adjoined to one of the four photodiodes and the common floating diffusion region. The four photodiodes are located within four different quadrants as defined employing a vertical line passing through a point within the common floating diffusion region as a center axis. The common floating diffusion region, a reset gate transistor, a source follower transistor, and a row select transistor are located within four different quadrants as defined employing a vertical line passing through a point within one of the photodiodes as an axis.
摘要翻译：图像传感器的像素结构包括具有共面且相邻的半导体表面的半导体材料部分，包括四个光电二极管，四个沟道区域和公共的浮动扩散区域。四个通道区域中的每一个直接邻接四个光电二极管和公共浮动扩散区域中的一个。四个光电二极管位于四个不同的象限内，如使用通过公共浮动扩散区域内的点作为中心轴的垂直线所限定的。公共浮动扩散区域，复位栅极晶体管，源极跟随器晶体管和行选择晶体管位于四个不同的象限内，如使用通过一个光电二极管内的点作为轴的垂直线所限定的。

2. 发明申请

US20110025892A1 IMAGE SENSOR PIXEL STRUCTURE EMPLOYING A SHARED FLOATING DIFFUSION 有权
标题翻译：图像传感器像素结构采用共享浮动扩展
公开(公告)号：US20110025892A1
公开(公告)日：2011-02-03
申请号：US12534427
申请日：2009-08-03
申请人： Jason D. Hibbeler , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel
发明人： Jason D. Hibbeler , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel
IPC分类号： H04N5/335 , H01L31/112 , G06F17/50
CPC分类号： H01L27/14609 , H01L27/14641 , H01L27/14643 , H04N5/37457
摘要： A pixel structure for an image sensor includes a semiconductor material portion having a coplanar and contiguous semiconductor surface and including four photodiodes, four channel regions, and a common floating diffusion region. Each of the four channel regions is directly adjoined to one of the four photodiodes and the common floating diffusion region. The four photodiodes are located within four different quadrants as defined employing a vertical line passing through a point within the common floating diffusion region as a center axis. The common floating diffusion region, a reset gate transistor, a source follower transistor, and a row select transistor are located within four different quadrants as defined employing a vertical line passing through a point within one of the photodiodes as an axis.
摘要翻译：图像传感器的像素结构包括具有共面且相邻的半导体表面的半导体材料部分，包括四个光电二极管，四个沟道区域和公共的浮动扩散区域。四个通道区域中的每一个直接邻接四个光电二极管和公共浮动扩散区域中的一个。四个光电二极管位于四个不同的象限内，如使用通过公共浮动扩散区域内的点作为中心轴的垂直线所限定的。公共浮动扩散区域，复位栅极晶体管，源极跟随器晶体管和行选择晶体管位于四个不同的象限内，如使用通过一个光电二极管内的点作为轴的垂直线所限定的。

3. 发明申请

US20090031263A1 METHOD AND SYSTEM FOR ANALYZING AN INTEGRATED CIRCUIT BASED ON SAMPLE WINDOWS SELECTED USING AN OPEN DETERMINISTIC SEQUENCING TECHNIQUE 有权
标题翻译：基于使用开放式确定性测序技术选择的样本窗口分析集成电路的方法和系统
公开(公告)号：US20090031263A1
公开(公告)日：2009-01-29
申请号：US11828728
申请日：2007-07-26
申请人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
发明人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.
摘要翻译：这里公开的是用于分析集成电路以确定该集成电路中的特定属性（即，物理或电气特性）的值的系统和相关方法的实施例。在实施例中，使用开放确定性测序技术来选择表示集成电路布局中的样本窗口中心的点序列。然后，为每个采样窗口确定特定属性的值，并累积结果，以推断整个集成电路布局的该特定属性的总体值。这种测序技术具有允许添加附加样品窗口和/或改变窗口的尺寸和形状而不妨碍样品质量的优点。

4. 发明申请

US20080195989A1 CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS 失效
标题翻译：基于内容的VLSI设计预测
公开(公告)号：US20080195989A1
公开(公告)日：2008-08-14
申请号：US12101599
申请日：2008-04-11
申请人： Robert J. Allen , Daria R. Dooling , Jason D. Hibbeler , Daniel N. Maynard , Sarah C. Prue , Ralph J. Williams
发明人： Robert J. Allen , Daria R. Dooling , Jason D. Hibbeler , Daniel N. Maynard , Sarah C. Prue , Ralph J. Williams
IPC分类号： G06F9/45
CPC分类号： G06F17/5045
摘要： An integrated circuit and program product for predicting yield of a VLSI design. An integrated circuit is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.
摘要翻译：一种用于预测VLSI设计产量的集成电路和程序产品。提供一种集成电路，包括用于通过电路类型识别和分组集成电路设计中包含的子电路的系统; 用于确定不同区域的临界面积值的关键区域计算系统，其中每个不同区域与电路类型相关联; 用于基于电路类型计算多个临界面积值的计数系统; 以及多个建模子系统，用于基于电路类型对所述多个提议中的每一个进行单独建模。

5. 发明授权

US07752589B2 Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design 失效
标题翻译：用于显示和修改集成电路设计的关键区域的方法，装置和计算机程序产品
公开(公告)号：US07752589B2
公开(公告)日：2010-07-06
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译：一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。

6. 发明授权

US07752580B2 Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique 有权
标题翻译：基于使用开放确定性测序技术选择的样本窗口来分析集成电路的方法和系统
公开(公告)号：US07752580B2
公开(公告)日：2010-07-06
申请号：US11828728
申请日：2007-07-26
申请人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
发明人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.
摘要翻译：这里公开的是用于分析集成电路以确定该集成电路中的特定属性（即，物理或电气特性）的值的系统和相关方法的实施例。在实施例中，使用开放确定性测序技术来选择表示集成电路布局中的样本窗口中心的点序列。然后，为每个采样窗口确定特定属性的值，并累积结果，以推断整个集成电路布局的该特定属性的总体值。这种测序技术具有允许添加附加样品窗口和/或改变窗口的尺寸和形状而不妨碍样品质量的优点。

7. 发明申请

US20080168414A1 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR DISPLAYING AND MODIFYING THE CRITICAL AREA OF AN INTEGRATED CIRCUIT DESIGN. 失效
标题翻译：用于显示和修改集成电路设计关键领域的方法，装置和计算机程序产品。
公开(公告)号：US20080168414A1
公开(公告)日：2008-07-10
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译：一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。

8. 发明授权

US07389480B2 Content based yield prediction of VLSI designs 有权
标题翻译：基于内容的VLSI设计的产量预测
公开(公告)号：US07389480B2
公开(公告)日：2008-06-17
申请号：US10908342
申请日：2005-05-09
申请人： Robert J. Allen , Daria R. Dooling , Jason D. Hibbeler , Daniel N. Maynard , Sarah C. Prue , Ralph J. Williams
发明人： Robert J. Allen , Daria R. Dooling , Jason D. Hibbeler , Daniel N. Maynard , Sarah C. Prue , Ralph J. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A system, method and program product for predicting yield of a VLSI design. A method is provided including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.
摘要翻译：一种用于预测VLSI设计产量的系统，方法和程序产品。提供了一种方法，包括以下步骤：通过类型识别和分组集成电路设计中包含的子电路; 计算集成电路设计中区域的关键面积值; 以及基于用于计算临界面积值的区域的类型将不同的屈服模型应用于临界区域值，其中每个产量模型依赖于类型。

9. 发明授权

US07661081B2 Content based yield prediction of VLSI designs 失效
标题翻译：基于内容的VLSI设计的产量预测
公开(公告)号：US07661081B2
公开(公告)日：2010-02-09
申请号：US12101599
申请日：2008-04-11
申请人： Robert J. Allen , Daria R. Dooling , Jason D. Hibbeler , Daniel N. Maynard , Sarah C. Prue , Ralph J. Williams
发明人： Robert J. Allen , Daria R. Dooling , Jason D. Hibbeler , Daniel N. Maynard , Sarah C. Prue , Ralph J. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An integrated circuit system and program product for predicting yield of a VLSI design. An integrated circuit system is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.
摘要翻译：一种用于预测VLSI设计产量的集成电路系统和程序产品。提供一种集成电路系统，包括用于通过电路类型识别和集成集成电路设计中所包含的子电路的系统; 用于确定不同区域的临界面积值的关键区域计算系统，其中每个不同区域与电路类型相关联; 用于基于电路类型计算多个临界面积值的计数系统; 以及多个建模子系统，用于基于电路类型对所述多个提议中的每一个进行单独建模。

10. 发明授权

US07398485B2 Yield optimization in router for systematic defects 失效
标题翻译：路由器产生优化系统缺陷
公开(公告)号：US07398485B2
公开(公告)日：2008-07-08
申请号：US11279262
申请日：2006-04-11
申请人： Jeanne P. Bickford , Markus T. Buehler , Jason D. Hibbeler , Juergen Koehl , Daniel N. Maynard
发明人： Jeanne P. Bickford , Markus T. Buehler , Jason D. Hibbeler , Juergen Koehl , Daniel N. Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify structure-specific mechanisms that impact IC yield. Next, the method establishes a structural identifier for each structure-specific mechanism, wherein the structural identifiers include wire codes, tags, and/or unique identifiers. Different structural identifiers are established for wires having different widths. Furthermore, the method establishes a weighting factor for each structure-specific mechanism, wherein higher weighting factors are established for structure-specific mechanisms comprising thick wires proximate to multiple thick wires. The method establishes the structural identifiers and the weighting factors for incidence of spacing between single wide lines, double wide lines, and triple wide lines and for incidence of wires above large metal lands. Subsequently, the router settings are modified based on the structural identifiers and the weighting factors to minimize systematic defects.
摘要翻译：本文的实施例提供了一种用于优化路由器设置以增加IC产量的方法和计算机程序产品。一种方法开始于检查IC生产线中的产量数据，以确定影响IC产量的结构特异性机制。接下来，该方法为每个结构特定机制建立结构标识符，其中结构标识符包括有线代码，标签和/或唯一标识符。针对具有不同宽度的电线建立了不同的结构标识符。此外，该方法为每个结构特定机构建立加权因子，其中针对包括靠近多个粗线的粗线的结构特定机构建立较高的加权因子。该方法建立了单宽线，双宽线和三宽线之间的间距发生的结构标识符和加权因子，以及大金属土地上电线的入射。随后，路由器设置基于结构标识符和权重因子进行修改，以最大限度地减少系统缺陷。

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